STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 112

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STM32W108CBU6

Manufacturer Part Number
STM32W108CBU6
Description
High-performance, IEEE 802.15.4 wireless system-on-chip
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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General-purpose timers
8.3
8.3.1
112/179
31
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15
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30
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14
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General-purpose timer (1 and 2) registers
Timer x control register 1 (TIMx_CR1)
Address offset: 0xE000 (TIM1) and 0xF000 (TIM2)
Reset value:
[6:5] TIM_CMS: Center-aligned Mode Selection
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13
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[7] TIM_ARBE: Auto-Reload Buffer Enable
[4] TIM_DIR: Direction
[3] TIM_OPM: One Pulse Mode
[2] TIM_URS: Update Request Source
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(TIM_DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy
register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy
register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy
register) are set both when the counter is counting up or down.
Note: Software may not switch from edge-aligned mode to center-aligned mode when the
0: Counter used as up-counter.
1: Counter used as down-counter.
0: Counter does not stop counting at the next update event.
1: Counter stops counting at the next update event (and clears the bit TIM_CEN).
0: When enabled, update interrupt requests are sent as soon as registers are updated (counter
overflow/underflow, setting the TIM_UG bit, or update generation through the slave mode
controller).
1: When enabled, update interrupt requests are sent only when the counter reaches overflow or
underflow.
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12
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counter is enabled (TIM_CEN=1).
27
11
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0x0000 0000
26
10
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25
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9
Doc ID 16252 Rev 2
24
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8
TIM_A
RBE
23
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7
22
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6
TIM_CMS
21
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5
STM32W108CB, STM32W108HB
TIM_D
20
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IR
4
TIM_O
PM
19
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3
TIM_U
RS
18
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2
TIM_U
DIS
17
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1
TIM_C
EN
16
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0

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