STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 116

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General-purpose timers
8.3.4
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Timer x event generation register (TIMx_EGR)
Address offset: 0xE014 (TIM1) and 0xF014 (TIM2)
Reset value:
[6:4] TIM_TS: Trigger Selection
[2:0] TIM_SMS: Slave Mode Selection
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[7] TIM_MSM: Master/Slave Mode
0: No action.
1: The effect of an event on the trigger input (TRGI) is delayed to allow exact synchronization
between the current timer and the slave (through TRGO). It is useful for synchronizing timers
on a single external event.
This bit field selects the trigger input used to synchronize the counter.
000 : Internal Trigger 0 (ITR0).
100 : TI1 Edge Detector (TI1F_ED).
101 : Filtered Timer Input 1 (TI1FP1).
110 : Filtered Timer Input 2 (TI2FP2).
111 : External Trigger input (ETRF).
Note: These bits must be changed only when they are not used (when TIM_SMS=000) to
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input.
000: Slave mode disabled.
If TIM_CEN = 1 then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1. Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
010: Encoder mode 2. Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
011: Encoder mode 3. Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
on the level of the other input.
100: Reset Mode. Rising edge of the selected trigger signal (TRGI) >reinitializes the counter
and generates an update of the registers.
101: Gated Mode. The counter clock is enabled when the trigger signal (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both starting and stopping
the counter are controlled.
110: Trigger Mode. The counter starts at a rising edge of the trigger TRGI (but it is not reset).
Only starting the counter is controlled.
111: External Clock Mode 1. Rising edges of the selected trigger (TRGI) clock the counter.
Note: Gated mode must not be used if TI1F_ED is selected as the trigger input
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avoid detecting spurious edges during the transition.
(TIM_TS=100). TI1F_ED outputs 1 pulse for each transition on TI1F, whereas gated
mode checks the level of the trigger signal.
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0x0000 0000
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9
Doc ID 16252 Rev 2
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8
23
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7
TIM_T
wo
22
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G
6
21
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5
STM32W108CB, STM32W108HB
TIM_C
C4G
wo
20
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4
TIM_C
C3G
wo
19
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3
TIM_C
C2G
wo
18
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2
TIM_C
C1G
wo
17
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1
TIM_U
wo
16
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G
0