STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 152

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Interrupts
10.3.5
152/179
INT_I
RQD
31
rw
15
rw
INT_I
RQC
30
rw
14
rw
Top-level active interrupts register (INT_ACTIVE)
Address offset: 0x0300
Reset value:
INT_I
RQB
[16] INT_DEBUG: Debug interrupt active.
[15] INT_IRQD: IRQD interrupt active.
[14] INT_IRQC: IRQC interrupt active.
[13] INT_IRQB: IRQB interrupt active.
[12] INT_IRQA: IRQA interrupt active.
[11] INT_ADC: ADC interrupt active.
[10] INT_MACRX: MAC receive interrupt active.
29
rw
13
rw
[8] INT_MACTMR: Write 1 to unpend MAC timer interrupt. (Writing 0 has no effect.)
[7] INT_SEC: Write 1 to unpend security interrupt. (Writing 0 has no effect.)
[6] INT_SC2: Write 1 to unpend serial controller 2 interrupt. (Writing 0 has no effect.)
[5] INT_SC1: Write 1 to unpend serial controller 1 interrupt. (Writing 0 has no effect.)
[4] INT_SLEEPTMR: Write 1 to unpend sleep timer interrupt. (Writing 0 has no effect.)
[3] INT_BB: Write 1 to unpend baseband interrupt. (Writing 0 has no effect.)
[2] INT_MGMT: Write 1 to unpend management interrupt. (Writing 0 has no effect.)
[1] INT_TIM2: Write 1 to unpend timer 2 interrupt. (Writing 0 has no effect.)
[0] INT_TIM1: Write 1 to unpend timer 1 interrupt. (Writing 0 has no effect.)
[9] INT_MACTX: MAC interrupt active.
[8] INT_MACTMR: MAC timer interrupt active.
[7] INT_SEC: Ssecurity interrupt active.
[6] INT_SC2: Serial controller 2 interrupt active.
[5] INT_SC1: Serial controller 1 interrupt active.
[4] INT_SLEEPTMR: Sleep timer interrupt active.
[3] INT_BB: Baseband interrupt active.
INT_I
RQA
28
12
rw
rw
INT_A
DC
27
11
rw
rw
0x0000 0000
INT_M
ACRX
26
10
rw
rw
INT_M
ACTX
25
rw
rw
9
Doc ID 16252 Rev 2
INT_M
ACTM
24
rw
rw
R
8
INT_S
EC
23
rw
rw
7
INT_S
C2
22
rw
rw
6
INT_SC
21
rw
rw
5
1
STM32W108CB, STM32W108HB
INT_S
LEEP
TMR
20
rw
rw
4
INT_B
19
rw
rw
3
B
INT_M
GMT
18
rw
rw
2
INT_TI
M2
17
rw
rw
1
INT_TI
INT_D
EBUG
M1
16
rw
rw
0