STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 86

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General-purpose timers
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In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit
generates an update event, but without setting the INT_TIMUIF flag. Thus no interrupt
request is sent. This avoids generating both update and capture interrupts when clearing the
counter on the capture event.
When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG
register) is set (unless TIM_USR is 1) and the following registers are updated:
●
●
Figure 16
frequencies when TIMx_ARR = 0x36.
Figure 16. Counter timing diagram, internal clock divided by 1
Figure 17. Counter timing diagram, internal clock divided by 4
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the
TIMx_ARR register) - 1 and generates a counter overflow event, then counts from the
autoreload value down to 1 and generates a counter underflow event. Then it restarts
counting from 0.
In this mode, the direction bit (TIM_DIR in the TIMx_CR1 register) cannot be written. It is
updated by hardware and gives the current direction of the counter.
The prescaler shadow register is reloaded with the buffer value (contents of the
TIMx_PSC register).
The auto-reload active register is updated with the buffer value (contents of the
TIMx_ARR register). The auto-reload is updated before the counter is reloaded, so that
the next period is the expected one.
and
Figure 17
show some examples of the counter behavior for different clock
Doc ID 16252 Rev 2
STM32W108CB, STM32W108HB