STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 12

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Description
1.2.6
1.2.7
1.2.8
1.2.9
12/179
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 20 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
●
●
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for
an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Boot from User Flash
Boot from System memory
Boot from embedded SRAM
V
externally through VDD pins.
V
and PLL (minimum voltage to be applied to V
V
V
registers (through power switch) when VDD is not present.
DD
SSA
DDA
BAT
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided
, V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
and V
DDA
SSA
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
must be connected to VDD and VSS, respectively.
Doc ID 16252 Rev 2
DDA
is 2.4 V when the ADC is used).
STM32W108CB, STM32W108HB