STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 113

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32W108CB, STM32W108HB
8.3.2
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Timer x control register 2 (TIMx_CR2)
Address offset: 0xE004 (TIM1) and 0xF004 (TIM2)
Reset value:
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[1] TIM_UDIS: Update Disable
[0] TIM_CEN: Counter Enable
[7] TIM_TI1S: TI1 Selection
0: An update event is generated as soon as a counter overflow occurs, a software update is
generated, or a hardware reset is generated by the slave mode controller. Shadow registers are
then loaded with their buffer register values.
1: An update event is not generated and shadow registers keep their value (TIMx_ARR,
TIMx_PSC, TIMx_CCRy). The counter and the prescaler are reinitialized if the TIM_UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled.
1: Counter enabled.
Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has
0: TI1M (input of the digital filter) is connected to TI1 input.
1: TI1M is connected to the TI_HALL inputs (XOR combination).
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been previously set by software. Trigger mode sets the TIM_CEN bit automatically
through hardware.
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0x0000 0000
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9
Doc ID 16252 Rev 2
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8
TIM_TI
1S
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7
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6
TIM_MMS
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5
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4
General-purpose timers
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3
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2
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1
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