STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 49

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32W108CB, STM32W108HB
6.1.4
6.1.5
Note:
6.1.6
Note:
Reset
A full chip reset is one due to power on (low or high voltage), the NRST pin, the watchdog, or
the SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows:
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nBOOTMODE
nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset
(NRST) or a power-on-reset of the always-powered domain (POR_HV). If nBOOTMODE is
asserted (pulled or driven low) when coming out of reset, the processor starts executing an
embedded serial boot loader instead of its normal program.
While in reset and during the subsequent power-on-reset startup delay (512 high-frequency
RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At
the end of this time, the STM32W108 samples nBOOTMODE: a high level selects normal
startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5
is configured as a floating input. The GPIO_BOOTMODE bit in the GPIO_DBGSTAT register
captures the state of nBOOTMODE so that software may act on this signal if required.
To avoid inadvertently asserting nBOOTMODE, PA5's capacitive load should not exceed
252 pF.
GPIO modes
Analog mode
Analog mode enables analog functions, and disconnects a pin from the digital input and
output logic. Only the following GPIO pins have analog functions:
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When an external timing source is required, a 32.768 kHz crystal is commonly connected to
PC6 and PC7. Alternatively, when PC7 is configured as a digital input, PC7 can accept a
digital external clock input.
When configured in analog mode:
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The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.
The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the
normal configuration for PA7.
The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial
Wire/JTAG access to override the normal configuration of PC0, PC2, PC3, and PC4.
PA4, PA5, PB5, PB6, PB7, and PC1 can be analog inputs to the ADC.
PB0 can be an external analog voltage reference input to the ADC, or it can output the
internal analog voltage reference from the ADC.
PC6 and PC7 can connect to an optional 32.768 kHz crystal.
The output drivers are disabled.
The internal pull-up and pull-down resistors are disabled.
The Schmitt trigger input is connected to a high logic level.
Reading GPIO_PxIN returns a constant 1.
Doc ID 16252 Rev 2
General-purpose input/outputs
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