STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 94

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General-purpose timers
Note:
8.1.6
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To detect missed captures reliably, read captured data in TIMxCCRy before checking the
missed capture/compare flag. This sequence avoids missing a capture that could happen
after reading the flag and before reading the data.
Software can generate IC interrupt requests by setting the corresponding TIM_CCyG bit in
the TIMx_EGR register.
PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
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For example, to measure the period in the TIMx_CCR1 register and the duty cycle in the
TIMx_CCR2 register of the PWM applied on TI1, use the following procedure depending on
CK_INT frequency and prescaler value:
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Enable capture from the counter into the capture register by setting the TIM_CC1E bit
in the TIMx_CCER register.
If needed, enable the related interrupt request by setting the INT_TIMCC1IF bit in the
INT_TIMxCFG register.
When an input capture occurs:
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Two ICy signals are mapped on the same TIy input.
These two ICy signals are active on edges with opposite polarity.
One of the two TIyFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
Select the active input for TIMx_CCR1: write the TIM_CC1S bits to 01 in the
TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP1, used both for capture in the TIMx_CCR1 and
counter clear, by writing the TIM_CC1P bit to 0 (active on rising edge).
Select the active input for TIMx_CCR2by writing the TIM_CC2S bits to 10 in the
TIMx_CCMR1 register (TI1 selected).
Select the active polarity for TI1FP2 (used for capture in the TIMx_CCR2) by writing the
TIM_CC2P bit to 1 (active on falling edge).
Select the valid trigger input by writing the TIM_TS bits to 101 in the TIMx_SMCR
register (TI1FP1 selected).
Configure the slave mode controller in reset mode by writing the TIM_SMS bits to 100
in the TIMx_SMCR register.
Enable the captures by writing the TIM_CC1E and TIM_CC2E bits to 1 in the
TIMx_CCER register.
The TIMx_CCR1 register gets the value of the counter on the active transition.
INT_TIMCC1IF flag is set (capture/compare interrupt flag). The missed
capture/compare flag INT_TIMMISSCC1IF in INT_TIMxMISS is also set if another
capture occurs before the INT_TIMCC1IF flag is cleared.
An interrupt may be generated if enabled by the INT_TIMCC1IF bit.
Doc ID 16252 Rev 2
STM32W108CB, STM32W108HB