STM32W108CBU6 STMICROELECTRONICS [STMicroelectronics], STM32W108CBU6 Datasheet - Page 73

• Manufacturer Part Number: STM32W108CBU6
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM32W108CB, STM32W108HB
7.7.2
15
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31
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14
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30
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Serial DMA status register (SCx_DMASTAT)
Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT)
Reset value:
13
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29
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[5] SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears
[4] SC_RXDMARST: Setting this bit resets the receive DMA. The bit clears
[3] SC_TXLODB: Setting this bit loads DMA transmit buffer B addresses and allows the
[2] SC_TXLODA: Setting this bit loads DMA transmit buffer A addresses and allows the
[1] SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the
[0] SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the
automatically.
automatically.
DMA controller to start processing transmit buffer B. If both buffer A and B are
loaded simultaneously, buffer A will be used first. This bit is cleared when DMA
completes. Writing a zero to this bit has no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
DMA controller to start processing transmit buffer A. If both buffer A and B are
loaded simultaneously, buffer A will be used first. This bit is cleared when DMA
completes. Writing a zero to this bit has no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
DMA controller to start processing receive buffer B. If both buffer A and B are loaded
simultaneously, buffer A will be used first. This bit is cleared when DMA completes.
Writing a zero to this bit has no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
DMA controller to start processing receive buffer A. If both buffer A and B are
loaded simultaneously, buffer A will be used first. This bit is cleared when DMA
completes. Writing a zero to this bit has no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
12
28
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11
27
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0x0000 0000
10
26
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25
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9
Doc ID 16252 Rev 2
24
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8
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23
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7
22
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rw
6
DMARS
SC_TX
21
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T
w
5
XDMA
SC_R
RST
20
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w
4
SC_TX
LODB
rw
19
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3
SC_TX
LODA
Serial interfaces
18
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2
SC_RX
LODB
17
rw
rw
1
73/179
SC_RX
LODA
rw
16
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0