DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet
DF2367VF33
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HD64F2367VF33
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DF2367VF33 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2368 Group 16 Hardware Manual Renesas 16-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of ...
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The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general ...
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In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. For the execution state of each instruction in this LSI, see appendix D, Bus State during Execution of Instructions. • In ...
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Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.3.3 Pin Functions 14 Table 1.2 Pin Functions 20 Table amended Pin No. Type Symbol TFP-120 QFP-128* 2 Power Supply V 2, 33* , 60, 6,39,66, cc 83, ...
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Item Page Revision (See Manual for Details) 3.4 Memory Map in Each 64 Operating Mode Figure 3.2 H8S/2368F Memory Map (2) Rev.6.00 Mar. 18, 2009 Page viii of lviii REJ09B0050-0600 Figure amended ROM: 512 kbytes RAM: 32 kbytes Mode 4 ...
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Item Page Revision (See Manual for Details) 3.4 Memory Map in Each 67 Operating Mode Figure 3.5 H8S/2364F Memory Map (1) 7.3.7 DMA Terminal 240 Control Register (DMATCR) 8.8.5 Chain Transfer 321 Figure amended RAM: 32 kbytes Modes 1 and ...
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Item Page Revision (See Manual for Details) 9.8.8 Pin Functions 370 371 372 9.9.5 Pin Functions 375 9.10.5 Pin Functions 379 9.11.5 Pin Functions 383 9.12.5 Pin Functions 387 Rev.6.00 Mar. 18, 2009 Page x of lviii REJ09B0050-0600 Table amended ...
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Item Page Revision (See Manual for Details) 9.13.4 Pin Functions 391 393 14.3.7 Serial Status 558 Register (SSR) Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Smart Card Interface 562 Mode (When SMIF in SCMR is 1) ...
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Item Page Revision (See Manual for Details) 14.3.9 Bit Rate Register 566 (BRR) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 14.4.4 SCI Initialization 580 (Asynchronous Mode) 14.6.2 SCI Initialization 596 (Clocked Synchronous Mode) 2 Section 15 I ...
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Item Page Revision (See Manual for Details) 2 15.3 Bus Control 634 Register A (ICCRA) Table 15.2 Transfer Rate 2 15.3 Bus Status 639 Register (ICSR) 15.4.5 Slave Receive 652 Operation Figure 15.12 Slave Receive Mode ...
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Item Page Revision (See Manual for Details) 15.4.7 Example of Use 655 Figure 15.15 Sample Flowchart for Master Receive Mode Figure 15.17 Sample 657 Flowchart for Slave Receive Mode Rev.6.00 Mar. 18, 2009 Page xiv of lviii REJ09B0050-0600 Figure amended ...
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Item Page Revision (See Manual for Details) 15.7 Usage Notes 660 bus interface 2 (IIC2) master receive mode 4. Limitations on transfer rate setting values when 2 using I C bus interface 2 (IIC2) in multi-master ...
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Item Page Revision (See Manual for Details) 20.8 Serial 788 Communication Interface Specification for Boot Mode (4) Inquiry and Selection States Figure 20.21 801 Programming Sequence (9) Programming/Erasing 802 State • Programming (b) 128-byte programming 24.2 Register Bits 855 25.1.2 ...
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Item Page Revision (See Manual for Details) 25.1.2 DC 876 Characteristics Table 25.4 Permissible Output Currents 25.2.2 DC 912 Characteristics Table 25.14 DC Characteristics (1) Table 25.16 Permissible 914 Output Currents Table amended Item Permissible output low SCL0, 1, SDA0, ...
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Item Page Revision (See Manual for Details) 25.3.2 DC 927 Characteristics Table 25.27 DC Characteristics Table 25.28 DC 928 Characteristics Table 25.29 Permissible 929 Output Currents Rev.6.00 Mar. 18, 2009 Page xviii of lviii REJ09B0050-0600 Table amended Item Symbol − ...
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Item Page Revision (See Manual for Details) 25.3.3 AC 930 Characteristics 25.3.3 AC 935 Characteristics Table 25.33 Bus Timing (2) Description deleted (Before) The clock, control signal, bus, DMAC, (After) The clock, control signal, bus, DMAC, and … Table amended ...
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All trademarks and registered trademarks are the property of their respective owners. Rev.6.00 Mar. 18, 2009 Page xx of lviii REJ09B0050-0600 ...
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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Arrangement in Each Operating Mode .......................................................... 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...................................................................................................................... 21 2.1 Features ............................................................................................................................. 21 ...
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Memory Indirect—@@aa:8 ................................................................................ 51 2.7.9 Effective Address Calculation ............................................................................. 52 2.8 Processing States............................................................................................................... 55 2.9 Usage Note........................................................................................................................ 56 2.9.1 Note on Bit Manipulation Instructions................................................................. 56 Section 3 MCU Operating Modes 3.1 Operating Mode Selection ................................................................................................ 57 3.2 Register Descriptions ...
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IRQ Enable Register (IER) .................................................................................. 95 5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 96 5.3.5 IRQ Status Register (ISR).................................................................................... 99 5.3.6 IRQ Pin Select Register (ITSR) ........................................................................... 100 5.3.7 Software Standby Release IRQ Enable Register (SSIER) ................................... 101 5.4 ...
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Refresh Time Constant Register (RTCOR) ......................................................... 144 6.4 Operation .......................................................................................................................... 144 6.4.1 Area Division....................................................................................................... 144 6.4.2 Bus Specifications................................................................................................ 146 6.4.3 Memory Interfaces ............................................................................................... 148 6.4.4 Chip Select Signals .............................................................................................. 149 6.5 Basic Bus Interface ........................................................................................................... 150 6.5.1 Data Size ...
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Operation ............................................................................................................. 209 6.11.2 Bus Transfer Timing ............................................................................................ 210 6.12 Bus Controller Operation in Reset .................................................................................... 211 6.13 Usage Notes ...................................................................................................................... 211 6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 211 6.13.2 External Bus Release Function and Software Standby ...
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Clearing Full Address Mode................................................................................ 286 7.6 Interrupt Sources............................................................................................................... 287 7.7 Usage Notes ...................................................................................................................... 288 7.7.1 DMAC Register Access during Operation........................................................... 288 7.7.2 Module Stop......................................................................................................... 289 7.7.3 Write Data Buffer Function ................................................................................. 289 TEND Output....................................................................................................... 290 7.7.4 Activation by Falling ...
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Software Activation ............................................................................................. 320 8.8 Usage Notes ...................................................................................................................... 321 8.8.1 Module Stop Mode Setting .................................................................................. 321 8.8.2 On-Chip RAM ..................................................................................................... 321 8.8.3 DTCE Bit Setting................................................................................................. 321 8.8.4 DMAC Transfer End Interrupt............................................................................. 321 8.8.5 Chain Transfer ..................................................................................................... 321 Section 9 ...
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Port 9 Register (PORT9)...................................................................................... 363 9.7.2 Pin Functions ....................................................................................................... 363 9.8 Port A................................................................................................................................ 364 9.8.1 Port A Data Direction Register (PADDR) ........................................................... 365 9.8.2 Port A Data Register (PADR).............................................................................. 366 9.8.3 Port A Register (PORTA).................................................................................... 366 9.8.4 Port A ...
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Port F................................................................................................................................. 388 9.13.1 Port F Data Direction Register (PFDDR) ............................................................ 389 9.13.2 Port F Data Register (PFDR) ............................................................................... 390 9.13.3 Port F Register (PORTF) ..................................................................................... 390 9.13.4 Pin Functions ....................................................................................................... 391 9.14 Port G ................................................................................................................................ 395 9.14.1 Port ...
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Input Clock Restrictions ...................................................................................... 477 10.10.3 Caution on Cycle Setting ..................................................................................... 478 10.10.4 Contention between TCNT Write and Clear Operations ..................................... 478 10.10.5 Contention between TCNT Write and Increment Operations.............................. 479 10.10.6 Contention between TGR Write and Compare Match ...
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Register Descriptions ........................................................................................................ 509 12.3.1 Timer Counter (TCNT)........................................................................................ 509 12.3.2 Time Constant Register A (TCORA)................................................................... 510 12.3.3 Time Constant Register B (TCORB) ................................................................... 510 12.3.4 Timer Control Register (TCR) ............................................................................ 510 12.3.5 Timer Control/Status Register (TCSR)................................................................ 512 12.4 Operation........................................................................................................................... ...
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Interrupts........................................................................................................................... 536 13.6 Usage Notes ...................................................................................................................... 536 13.6.1 Notes on Register Access..................................................................................... 536 13.6.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 538 13.6.3 Changing Value of CKS2 to CKS0...................................................................... 538 13.6.4 Switching between Watchdog Timer Mode and ...
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Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 602 14.7 Operation in Smart Card Interface Mode .......................................................................... 604 14.7.1 Pin Connection Example...................................................................................... 604 14.7.2 Data Format (Except for Block Transfer Mode) .................................................. 605 14.7.3 Block Transfer Mode ...
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Master Transmit Operation .................................................................................. 644 15.4.3 Master Receive Operation.................................................................................... 646 15.4.4 Slave Transmit Operation .................................................................................... 648 15.4.5 Slave Receive Operation...................................................................................... 650 15.4.6 Noise Canceler..................................................................................................... 653 15.4.7 Example of Use.................................................................................................... 653 15.5 Interrupt Request............................................................................................................... 658 15.6 Bit Synchronous Circuit.................................................................................................... 658 ...
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Setting for Module Stop Mode............................................................................. 686 17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 686 Section 18 RAM .................................................................................................................. 687 Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.1 Features ............................................................................................................................. 689 19.2 Mode Transitions .............................................................................................................. 691 19.3 Block ...
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Programming/Erasing Interface Parameter .......................................................... 735 20.3.3 Flash Vector Address Control Register (FVACR)............................................... 747 20.4 On-Board Programming Mode ......................................................................................... 748 20.4.1 Boot Mode ........................................................................................................... 748 20.4.2 User Program Mode............................................................................................. 753 20.4.3 User Boot Mode................................................................................................... 764 20.4.4 Procedure Program and Storable ...
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Sleep Mode .......................................................................................................... 830 23.2.3 Software Standby Mode....................................................................................... 831 23.2.4 Hardware Standby Mode ..................................................................................... 834 23.2.5 Module Stop Mode .............................................................................................. 835 23.2.6 All-Module-Clocks-Stop Mode ........................................................................... 836 23.3 φ Clock Output Control..................................................................................................... 836 23.4 Usage Notes ...................................................................................................................... 837 23.4.1 I/O ...
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Appendix ............................................................................................................................. 941 A. I/O Port States in Each Pin State....................................................................................... 941 B. Product Lineup.................................................................................................................. 949 C. Package Dimensions ......................................................................................................... 950 D. Bus State during Execution of Instructions....................................................................... 952 Index ............................................................................................................................. 975 Rev.6.00 Mar. 18, 2009 Page xxxviii of lviii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2367F, H8S/2365, and H8S/2363........................ Internal Block Diagram of H8S/2368 0.18 μm F-ZTAT Group............................. Figure 1.2 Figure 1.3 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363 .................................. Pin Arrangement of H8S/2368 0.18 μm ...
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Figure 3.14 H8S/2365 Memory Map (2) ................................................................................... 76 Figure 3.15 H8S/2363 Memory Map......................................................................................... 77 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled).......................... 82 Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)......................... 83 ...
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Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended .................... 164 Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)........................................... 168 Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle (RAST ...
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Figure 6.52 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0)......................................................................... 199 Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, ...
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Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer.... 279 Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer....... 280 Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function................. ...
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Figure 10.10 Example of Synchronous Operation Setting Procedure ......................................... 446 Figure 10.11 Example of Synchronous Operation....................................................................... 447 Figure 10.12 Compare Match Buffer Operation.......................................................................... 448 Figure 10.13 Input Capture Buffer Operation ............................................................................. 448 Figure 10.14 Example of Buffer Operation Setting Procedure.................................................... ...
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Figure 10.50 Contention between TGR Write and Input Capture ............................................... 482 Figure 10.51 Contention between Buffer Register Write and Input Capture............................... 483 Figure 10.52 Contention between Overflow and Counter Clearing ............................................ 483 Figure 10.53 Contention between TCNT Write and Overflow.................................................... ...
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Section 14 Serial Communication Interface (SCI, IrDA) Figure 14.1 Block Diagram of SCI............................................................................................ 543 Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)............................................................................................ 576 Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... ...
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Figure 14.31 Timing for Fixing Clock Output Level................................................................... 614 Figure 14.32 Clock Halt and Restart Procedure .......................................................................... 615 Figure 14.33 Block Diagram of IrDA.......................................................................................... 616 Figure 14.34 IrDA Transmit/Receive Operations........................................................................ 617 Figure 14.35 Example of Synchronous Transmission Using DTC.............................................. 623 ...
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Section 17 D/A Converter Figure 17.1 Block Diagram of D/A Converter .......................................................................... 682 Figure 17.2 Example of D/A Converter Operation.................................................................... 686 Section 19 Flash Memory (0.35-μm F-ZTAT Version) Figure 19.1 Block Diagram of Flash Memory........................................................................... 690 Figure 19.2 Flash Memory ...
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Section 21 Mask ROM Figure 21.1 Block Diagram of 256-kbyte Mask ROM (HD6432365)....................................... 811 Section 22 Clock Pulse Generator Figure 22.1 Block Diagram of Clock Pulse Generator .............................................................. 813 Figure 22.2 Connection of Crystal Oscillator (Example) .......................................................... 816 Figure 22.3 ...
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Figure 25.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1).............. 899 Figure 25.22 External Bus Release Timing ................................................................................. 900 Figure 25.23 External Bus Request Output Timing..................................................................... 900 Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access................................. 902 Figure ...
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Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ Table 1.2 Pin Functions.......................................................................................................... 14 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ 37 Table 2.2 Operation Notation ................................................................................................. 38 Table 2.3 Data Transfer Instructions ...................................................................................... 39 Table 2.4 ...
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Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... 121 Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ........................................ 147 Table 6.3 Data Buses Used and Valid Strobes ....................................................................... 152 Table 6.4 Relation between Settings of Bits ...
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Table 9.6 MOS Input Pull-Up States (Port E) ........................................................................ 388 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions........................................................................................................ 402 Table 10.2 Pin Configuration ................................................................................................... 405 Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 409 Table 10.4 ...
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Section 11 Programmable Pulse Generator (PPG) Table 11.1 Pin Configuration ................................................................................................... 487 Section 12 8-Bit Timers (TMR) Table 12.1 Pin Configuration ................................................................................................... 509 Table 12.2 Clock Input to TCNT and Count Condition ........................................................... 512 Table 12.3 8-Bit Timer Interrupt Sources ...
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Table 16.2 Analog Input Channels and Corresponding ADDR Registers................................ 665 Table 16.3 A/D Conversion Time (Single Mode) .................................................................... 672 Table 16.4 A/D Conversion Time (Scan Mode)....................................................................... 672 Table 16.5 A/D Converter Interrupt Source ............................................................................. 673 Table 16.6 Analog Pin Specifications ...
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Section 22 Clock Pulse Generator Table 22.1 Damping Resistance Value .................................................................................... 816 Table 22.2 Crystal Oscillator Characteristics ........................................................................... 817 Table 22.3 External Clock Input Conditions............................................................................ 818 Section 23 Power-Down Modes Table 23.1 Operating Modes and Internal States of the LSI ...
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Table 25.30 Clock Timing.......................................................................................................... 930 Table 25.31 Control Signal Timing............................................................................................ 931 Table 25.32 Bus Timing (1) ....................................................................................................... 932 Table 25.33 Bus Timing (2) ....................................................................................................... 934 Table 25.34 DMAC Timing ....................................................................................................... 935 Table 25.35 Timing of On-Chip Peripheral Modules................................................................. 936 Table ...
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Rev.6.00 Mar. 18, 2009 Page lviii of lviii REJ09B0050-0600 ...
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Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions DMA controller (DMAC) Data transfer controller ...
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Section 1 Overview • On-chip memory ROM Type Model Flash memory version HD64F2368F HD64F2367F HD64F2364 HD64F2362F HD64F2361 HD64F2360 Masked ROM version HD6432365 ROMless version HD6412363 • General I/O ports I/O pins: 83 Input-only pins: 11 • Supports various power-down states ...
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Block Diagram Figures 1.1 and 1.2 show the internal block diagrams of this LSI. MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI φ PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/CS6/LCAS PF1/CS5/UCAS PF0/WAIT/OE PG6/BREQ PG5/BACK PG4/CS4/BREQO PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 ...
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Section 1 Overview MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI φ PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/CS6/LCAS PF1/CS5/UCAS PF0/WAIT/OE PG6/BREQ PG5/BACK PG4/CS4/BREQO PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 P85/SCK3 P83/RxD3 P81/TxD3 Figure 1.2 Internal Block Diagram of H8S/2368 0.18 ...
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Pin Description 1.3.1 Pin Arrangement Figures 1.3 to 1.5 show the pin arrangements of this LSI. 91 PG2/CS2/RAS2 92 PG3/CS3/RAS3 Vref 95 P40/AN0/(IRQ0) 96 P41/AN1/(IRQ1) 97 P42/AN2/(IRQ2) 98 P43/AN3/(IRQ3) 99 P44/AN4/(IRQ4) 100 P45/AN5/(IRQ5) 101 P46/AN6/(IRQ6) ...
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Section 1 Overview 91 PG2/CS2/RAS2 92 PG3/CS3/RAS3 Vref 95 P40/AN0/(IRQ0) 96 P41/AN1/(IRQ1) 97 P42/AN2/(IRQ2) 98 P43/AN3/(IRQ3) 99 P44/AN4/(IRQ4) 100 P45/AN5/(IRQ5) 101 P46/AN6/(IRQ6) 102 P47/AN7/(IRQ7) 103 P94/AN12/DA2 104 P95/AN13/DA3 105 AV SS 106 PG4/CS4/BREQO 107 PG5/BACK 108 ...
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AV 103 CC Vref 104 P40/AN0/(IRQ0) 105 P41/AN1/(IRQ1) 106 P42/AN2/(IRQ2) 107 P43/AN3/(IRQ3) 108 P44/AN4/(IRQ4) 109 P45/AN5/(IRQ5) 110 P46/AN6/(IRQ6) 111 P47/AN7/(IRQ7) 112 P94/AN12/DA2 113 P95/AN13/DA3 114 AV 115 SS PG4/CS4/BREQO 116 PG5/BACK 117 PG6/BREQ 118 P50/TxD2/IRQ0 119 P51/RxD2/IRQ1 120 P52/SCK2/IRQ2 121 ...
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Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No. QFP-128 * 1 TFP-120 Mode MD2 2 6 Vcc ...
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Pin No. QFP-128 * 1 TFP-120 Mode PA7/A23/CS7/ IRQ7 30 34 EMLE ⎯ 35 Vss ⎯ 36 Vss WDTOVF NMI * P10/PO8/ TIOCA0/ ...
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Section 1 Overview Pin No. QFP-128 * 1 TFP-120 Mode P23/PO3/ TIOCD3/TMCI1/ TxD4 46 52 P24/PO4/ TIOCA4/TMO0/ RxD4 47 53 P25/PO5/ TIOCB4/TMO1 48 54 P26/PO6/ TIOCA5 49 55 P27/PO7/ TIOCB5 50 56 P85/SCK3 ...
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Pin No. QFP-128 * 1 TFP-120 Mode D15 69 77 PF0/WAIT/ PF1/CS5/ UCAS 71 79 PF2/CS6/ LCAS 72 80 PF3/LWR HWR PF6/ PLLVcc RES 77 85 ...
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Section 1 Overview Pin No. QFP-128 * 1 TFP-120 Mode 1 94 104 Vref 95 105 P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0) P40/AN0/(IRQ0 106 P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1) P41/AN1/(IRQ1 107 P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2) P42/AN2/(IRQ2 108 ...
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Pin No. QFP-128 * 1 TFP-120 Mode 1 ⎯ 3 Vss ⎯ 4 Vss Notes: 1. Not supported by the H8S/2368 0.18 μm F-ZTAT Group. pin in the H8S/2368 0.18 μm F-ZTAT Group. 2. Used as the V CL Pin ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol TFP-120 Power Supply V 2, 33 17, 22, ss 58, 80, 87 PLLV 76 CC PLLV 78 SS VCL 33* Clock ...
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Pin No. Type Symbol TFP-120 System control RES 77 STBY 88 EMLE 30 Address bus A23 23 18 Data bus D15 61, D0 59, 57 ...
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Section 1 Overview Pin No. Type Symbol TFP-120 BACK Bus control 107 UCAS 70 LCAS 71 RAS2 91 RAS3 92 WAIT 69 OE 69, (OE) 113 Interrupt NMI 32 signals IRQ7 26, IRQ0 112 to 109, (IRQ7) ...
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Pin No. Type Symbol TFP-120 16-bit timer TCLKD 41, pulse unit (TPU) TCLKC 39, TCLKB 37, TCLKA 36 TIOCA0 34, TIOCB0 35, TIOCC0 36, TIOCD0 37 TIOCA1 38, TIOCB1 39 TIOCA2 40, TIOCB2 41 TIOCA3 42, TIOCB3 43, TIOCC3 44, ...
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Section 1 Overview Pin No. Type Symbol TFP-120 Serial TxD4 45, communication TxD3 86, interface(SCI)/ TxD2 109, smart card TxD1 117, interface (SCI_0 TxD0/ 118 with IrDA IrTxD function) RxD4 46, RxD3 85, RxD2 110, RxD1 115, RxD0/ 116 IrRxD ...
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Pin No. Type Symbol TFP-120 A/D converter, Vref 94 D/A converter I/O ports P17 to P1041 to 34 P27 to P2049 to 42 P35 to P30113 to 118 P47 to P40102 to 95 P53 to P50112 to 109 P85, 50, ...
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Section 1 Overview Pin No. Type Symbol TFP-120 I/O ports PG6 to 108 to 106, PG0 Notes: 1. Not supported by the H8S/2368 0.18 μm F-ZTAT Group. 2. VCL on the H8S/2368 0.18 µm F-ZTAT Group. Do ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU ⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) ⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes ⎯ Normal mode * ⎯ Advanced mode Note: * For this ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's ...
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Note: For this LSI, normal mode is not available. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode) SP (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not ...
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Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC bit extended control register (EXR), ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Bit Bit Name Initial Value Undefined 5 H Undefined 4 U Undefined 3 N Undefined 2 Z Undefined 1 V Undefined 0 C Undefined R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI ...
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Section 2 CPU 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 LDM, STM MOVFPE ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register ...
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Table 2.3 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions Instruction Size * 1 Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data ...
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Instruction Size * 1 Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size * Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. ...
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Table 2.7 Bit Manipulation Instructions Instruction Size * Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Section 2 CPU Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B – else next ≠ 0 then EEPMOV.W – else next: Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) Rev.6.00 ...
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Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate ...
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Section 2 CPU 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum ...
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Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data ...
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Section 2 CPU Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, refer to section 4, Exception Handling odd address ...
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Table 2.13 Effective Address Calculation Addressing Mode and Instruction Format Register direct (Rn) Register indirect (@ERn) Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ •Register indirect with pre-decrement @-ERn Effective Address Calculation General register contents General register ...
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Section 2 CPU Addressing Mode and Instruction Format Absolute address Immediate Note: * For this LSI, normal mode is not available. Rev.6.00 Mar. 18, 2009 Page 54 of 980 REJ09B0050-0600 Effective Address Calculation PC contents Sign extension Memory contents Memory ...
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Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU ...
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Section 2 CPU Bus-released state Exception handling state RES = High 1 Reset state* Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has six operating modes (modes and 7). Modes and 7 are available in the H8S/2368 0.18 μm F-ZTAT Group flash memory version. Modes ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this ...
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Bit Bit Name Initial Value − All 1 − All 0 3 FLSHE 0 − − 1 EXPE 0 RAME 1 Section 3 MCU Operating Modes R/W Descriptions R/W Reserved R/W The initial value ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D ...
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In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to 1. 3.3.5 Mode 5 This mode is a user boot mode of the flash memory. This mode is the same as mode ...
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Section 3 MCU Operating Modes 3.3.7 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Mode Port A PA7 to PA5 /A PA4 to ...
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Memory Map in Each Operating Mode Figures 3.1 to 3.15 show memory maps for each product. RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address H'FF4000 external address H'FFC000 Reserved area * ...
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Section 3 MCU Operating Modes ROM: 512 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'080000 External address space H'FF4000 On-chip RAM/ external address space* 1 H'FFC000 Reserved area * 4 H'FFD000 External ...
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RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 Reserved area * H'FF6000 On-chip RAM/ external address space* H'FFC000 Reserved area * H'FFC800 External address space H'FFFC00 Internal I/O registers H'FFFF00 ...
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Section 3 MCU Operating Modes (Expanded mode with on-chip ROM enabled) H'000000 H'060000 H'FF4000 H'FF6000 H'FFC000 H'FFC800 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Notes: 1. This area is specified as ...
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RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 On-chip RAM/ external address space* H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 ...
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Section 3 MCU Operating Modes ROM: 384 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'060000 Reserved area * 4 H'080000 External address space H'FF4000 On-chip RAM/ external address space* 1 H'FFC000 Reserved ...
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RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 On-chip RAM/ external address space* H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 ...
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area * 4 H'060000 External address space H'FF4000 On-chip RAM/ external address space* 1 H'FFC000 Reserved ...
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RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 Reserved area * H'FF6000 On-chip RAM/ external address space* H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 ...
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area * 4 H'080000 External address space H'FF4000 Reserved area * 4 H'FF6000 On-chip RAM/ external ...
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RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 Reserved area * H'FF8000 On-chip RAM/ external address space* H'FFC000 Reserved area * H'FFD000 External address space H'FFFC00 Internal I/O registers H'FFFF00 ...
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Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area * 4 H'080000 External address space H'FF4000 Reserved area * 4 H'FF8000 On-chip RAM/ external ...
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RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF4000 Reserved area * H'FF8000 On-chip RAM/ external address space* H'FFC000 Reserved area * H'FFC800 External address space H'FFFC00 Internal I/O registers H'FFFF00 ...
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Section 3 MCU Operating Modes Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area. 2. When EXPE = 1, external address space with RAME = 0, on-chip RAM with RAME = 1. When EXPE ...
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H'000000 H'FF8000 H'FFC000 H'FFC800 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR not access a reserved area. Figure 3.15 H8S/2363 Memory Map ...
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Section 3 MCU Operating Modes Rev.6.00 Mar. 18, 2009 Page 78 of 980 REJ09B0050-0600 ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more ...
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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Exception Source Power-on reset Manual reset * 3 Reserved for system use Trace Interrupt (direct transition Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use ...
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Exception Source Reserved for system use Internal interrupt * 4 Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not available in this LSI reserved for system use. 4. For details of ...
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Section 4 Exception Handling φ Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ...
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Address bus , D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states ...
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Section 4 Exception Handling Consequently, on-chip peripheral module registers cannot be read from or written to. Register reading and writing is enabled when module stop mode is exited. 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode ...
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The interrupt mask bit is updated and the T bit is cleared vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program ...
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Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes (b) Advanced Modes Notes: 1. Ignored on return. 2. Normal modes ...
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Usage Notes When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack ...
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Section 4 Exception Handling Rev.6.00 Mar. 18, 2009 Page 88 of 980 REJ09B0050-0600 ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMI input NMI input unit IRQ input unit IRQ input SSIER Internal interrupt sources SWDTEND to IICI1 Interrupt controller Legend: ISCRL: IRQ sense ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ7 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value − All 0 5 INTM1 0 4 INTM0 0 3 NMIEG 0 ...
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Interrupt Priority Registers (IPRA to IPRK) IPR are eleven 16-bit readable/writable registers that set priorities (levels for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 6 IPR6 1 5 IPR5 1 4 IPR4 1 − IPR2 1 1 IPR1 1 0 IPR0 1 Rev.6.00 Mar. 18, 2009 Page 94 of 980 REJ09B0050-0600 R/W ...
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IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value − All IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 ...
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Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Register L (ISCRL) ISCRL select the source that generates an interrupt request at pins IRQ7 to IRQ0. Bit Bit Name Initial Value 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 ...
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Bit Bit Name Initial Value 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 Section 5 Interrupt Controller R/W Description R/W IRQ4 Sense Control B R/W IRQ4 Sense Control A 00: ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 Rev.6.00 Mar. 18, 2009 Page 98 of 980 REJ09B0050-0600 R/W Description R/W IRQ1 Sense Control B R/W IRQ1 Sense ...
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IRQ Status Register (ISR) ISR is an IRQ7 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value − All 0 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F ...
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Section 5 Interrupt Controller 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ7 to IRQ0. Bit Bit Name Initial Value − All 0 7 ITS7 0 6 ITS6 0 5 ITS5 0 4 ITS4 0 ...
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Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value — All 0 7 SSI7 0 6 SSI6 0 5 SSI5 ...
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Section 5 Interrupt Controller When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in the interrupt ...
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Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number Refresh CMI 35 controller — Reserved for 36 system use 37 A/D ADI 38 — Reserved for 39 system use TPU_0 TGI0A 40 TGI0B 41 TGI0C 42 TGI0D ...
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Origin of Interrupt Interrupt Vector Source Source Number TPU_4 TGI4A 64 TGI4B 65 TCI4V 66 TCI4U 67 TPU_5 TGI5A 68 TGI5B 69 TCI5V 70 TCI5U 71 TMR_0 CMIA0 72 CMIB0 73 OVI0 74 — Reserved for 75 system use TMR_1 ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number SCI_1 ERI1 92 RXI1 93 TXI1 94 TEI1 95 SCI_2 ERI2 96 RXI2 97 TXI2 98 TEI2 99 SCI_3 ERI3 100 RXI3 101 TXI3 102 TEI3 103 SCI_4 ...
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Origin of Interrupt Interrupt Vector Source Source Number — Reserved for 120 system use 121 122 123 124 125 126 127 Note: Lower 16 bits of the start address. * Vector Address * Advanced Mode IPR H'01E0 IPRK2 to IPRK0 ...
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Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 5.3 Flowchart of Procedure ...
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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the ...
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Program execution status Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address ...
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Figure 5.5 Interrupt Exception Handling Section 5 Interrupt Controller Rev.6.00 Mar. 18, 2009 Page 113 of 980 REJ09B0050-0600 ...
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Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in ...
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Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch S I Branch address read S J Stack manipulation S K Legend: m: Number of wait states in an external device access. 5.6.5 DTC and DMAC ...
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Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit ...
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Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is ...
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Section 5 Interrupt Controller 5.7.6 Note on IRQ Status Register (ISR) Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from ISR after a reset and then write 0 ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus masters—the CPU, ...
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Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1. Internal address bus Internal bus master bus request signal Internal bus master bus acknowledge signal Internal bus control signals CPU bus request signal ...
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Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Address strobe Read High write Low write Chip select 0 Chip select 1 Chip select 2/row address strobe 2 Chip select 3/row ...
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Section 6 Bus Controller (BSC) Name Lower column address strobe Output enable Wait Bus request Bus request acknowledge Bus request output Data transfer acknowledge 1 (DMAC) Data transfer acknowledge 0 (DMAC) 6.3 Register Descriptions The bus controller has the following ...
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Refresh control register (REFCR) • Refresh timer counter (RTCNT) • Refresh time constant register (RTCOR) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. ...
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Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. • WTCRAH Bit ...
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Bit Bit Name Initial Value 10 W62 1 9 W61 1 8 W60 1 • WTARAL Bit Bit Name Initial Value − W52 1 5 W51 1 4 W50 1 Section 6 Bus Controller (BSC) R/W Description ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value − W42 1 1 W41 1 0 W40 1 Rev.6.00 Mar. 18, 2009 Page 126 of 980 REJ09B0050-0600 R/W Description R Reserved This bit is always read ...
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WTCRBH Bit Bit Name Initial Value − W32 1 13 W31 1 12 W30 1 − W22 1 9 W21 1 8 W20 1 Section 6 Bus Controller (BSC) R/W Description R Reserved ...
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Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value − W12 1 5 W11 1 4 W10 1 − W02 1 1 W01 1 0 W00 1 Rev.6.00 Mar. 18, 2009 ...
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Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value 7 RDN7 0 6 RDN6 0 5 RDN5 0 4 RDN4 0 ...
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Section 6 Bus Controller (BSC) CS Assertion Period Control Registers H, L (CSACRH, CSACRL) 6.3.5 CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals ...
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Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space Bus cycle and RDNn = 0) Rev.6.00 Mar. 18, 2009 Page ...
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Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM ...
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Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 10 ICIS0 1 9 WDBE 0 8 WAITE 0 − All 0 2 ICIS2 0 − 1 and 0 0 Rev.6.00 Mar. 18, 2009 Page 134 of ...
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DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Bit Bit Name Initial Value 15 OEE 0 14 RAST 0 − CAST 0 − Section 6 Bus Controller (BSC) R/W ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 10 RMTS2 0 9 RMTS1 0 8 RMTS0 Rev.6.00 Mar. 18, 2009 Page 136 of 980 REJ09B0050-0600 R/W Description R/W DRAM Space Select R/W These bits ...
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Bit Bit Name Initial Value 6 RCDM 0 5 DDS 0 − 4 and All 0 3 Section 6 Bus Controller (BSC) R/W Description RAS Down Mode R/W When access to DRAM space is interrupted by an access to normal ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 2 MXC2 0 1 MXC1 0 0 MXC0 0 Legend: ×: Don't care Rev.6.00 Mar. 18, 2009 Page 138 of 980 REJ09B0050-0600 R/W Description R/W Address Multiplex Select R/W These ...
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Address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) Bus cycle Row address Rev.6.00 Mar. 18, 2009 Page ...
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Section 6 Bus Controller (BSC) 6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM interface bus specifications. Bit Bit Name Initial Value 7 DRMI 0 − TPC1 0 4 TPC0 ...