DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 800
DF2367VF33
Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33
HD64F2367VF33
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Section 20 Flash Memory (0.18-μm F-ZTAT Version)
This parameter indicates the return value of the initialization result.
Bit
7 to 2
1
0
(3)
When flash memory is programmed, the programming destination address on the user MAT must
be passed to the programming program in which the program data is downloaded.
1. The start address of the programming destination on the user MAT must be stored in a general
2. The program data for the user MAT must be prepared in the consecutive area. The program
For details on the program processing procedure, see section 20.4.2, User Program Mode.
Rev.6.00 Mar. 18, 2009 Page 740 of 980
REJ09B0050-0600
(c) Flash pass/fail parameter (FPFR: general register R0L of CPU)
register ER1. This parameter is called as FMPAR (flash multipurpose address area parameter).
Since the program data is always in units of 128 bytes, the lower eight bits (A7 to A0) must be
H'00 or H'80 as the boundary of the programming start address on the user MAT.
data must be in the consecutive space which can be accessed by using the MOV.B instruction
of the CPU and in other than the flash memory space.
When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be
prepared by filling with the dummy code H'FF.
The start address of the area in which the prepared program data is stored must be stored in a
general register ER0. This parameter is called as FMPDR (flash multipurpose data destination
area parameter).
Programming Execution
Bit
Name
⎯
FQ
SF
Initial
Value
⎯
⎯
⎯
R/W
⎯
R/W
R/W
Description
Unused
Return 0
Frequency Error Detect
Returns the check result whether the specified operating
frequency of the CPU is in the range of the supported
operating frequency.
0: Setting of operating frequency is normal
1: Setting of operating frequency is abnormal
Success/Fail
Indicates whether initialization is completed normally.
0: Initialization is ended normally (no error)
1: Initialization is ended abnormally (error occurs)
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