DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 93

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

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Manufacturer:
Renesas Electronics America
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Manufacturer:
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Bit
7
6
5
4
3
2
1
0
Bit Name
I
UI
H
U
N
Z
V
C
1
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Initial Value
R/W Description
R/W Interrupt Mask Bit
R/W User Bit or Interrupt Mask Bit
R/W Half-Carry Flag
R/W User Bit
R/W Negative Flag
R/W Zero Flag
R/W Overflow Flag
R/W Carry Flag
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
at the start of an exception-handling sequence. For details,
refer to section 5, Interrupt Controller.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
For this LSI, Interrupt Mask Bit is not available.
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Stores the value of the most significant bit of data as a sign
bit.
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.
Set to 1 when an arithmetic overflow occurs, and cleared to
0 otherwise.
Set to 1 when a carry occurs, and cleared to 0 otherwise.
Used by:
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to indicate a carry
Rev.6.00 Mar. 18, 2009 Page 33 of 980
REJ09B0050-0600
Section 2 CPU

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