DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 561

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

11.4.5
Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output.
PPG setup
TPU setup
TPU setup
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
Sample Setup Procedure for Non-Overlapping Pulse Output
Set non-overlapping groups
Set counting operation
Select interrupt request
Select TGR functions
Set initial output data
Select output trigger
Enable pulse output
Compare match A?
Non-overlapping
Set TGR values
Set next pulse
Set next pulse
Start counter
pulse output
output data
output data
Yes
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
Section 11 Programmable Pulse Generator (PPG)
[1] Set TIOR to make TGRA and
[2] Set the pulse output trigger period
[3] Select the counter clock source
[4] Enable the TGIA interrupt in TIER.
[5] Set the initial output values in
[6] Set the DDR and NDER bits for the
[7] Select the TPU compare match
[8] In PMR, select the groups that will
[9] Set the next pulse output values in
[10] Set the CST bit in TSTR to 1 to
[11] At each TGIA interrupt, set the next
Rev.6.00 Mar. 18, 2009 Page 501 of 980
TGRB an output compare registers
(with output disabled)
in TGRB and the non-overlap
period in TGRA.
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR2 to CCLR0.
The DTC or DMAC can also be set
up to transfer data to NDR.
PODR.
pins to be used for pulse output to
1.
event to be used as the pulse
output trigger in PCR.
operate in non-overlap mode.
NDR.
start the TCNT counter.
output values in NDR.
REJ09B0050-0600