DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 208

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 6 Bus Controller (BSC)
6.4.3
Memory Interfaces
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on a synchronous DRAM interface that allows direct connection of
synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The
interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and an area for which the
burst ROM interface is designated functions as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external space, and in expanded mode with on-chip ROM
disabled, all of area 0 is external space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Area 1: In externally expanded mode, all of area 1 is external space.
When area 1 external space is accessed, the CS1 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 1.
Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Basic bus interface, or DRAM interface can be selected for areas 2 to 5. With the DRAM
interface, signals CS2 and CS3 are used as RAS signals.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM
space.
Area 6: In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Rev.6.00 Mar. 18, 2009 Page 148 of 980
REJ09B0050-0600