DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 42

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2367VF33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 3.14 H8S/2365 Memory Map (2) ................................................................................... 76
Figure 3.15 H8S/2363 Memory Map......................................................................................... 77
Section 4 Exception Handling
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Section 6 Bus Controller (BSC)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10 Bus Timing for 8-Bit, 3-State Access Space .......................................................... 154
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access).......... 155
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)........... 156
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ............................... 157
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access).......... 158
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)........... 159
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ............................... 160
Figure 6.17 Example of Wait State Insertion Timing................................................................ 162
Figure 6.18 Example of Read Strobe Timing ............................................................................ 163
Rev.6.00 Mar. 18, 2009 Page xl of lviii
REJ09B0050-0600
Reset Sequence (Advanced Mode with On-Chip ROM Disabled)......................... 83
Read Strobe Negation Timing (Example of 3-State Access Space) ....................... 129
Access Sizes and Data Alignment Control (16-bit Access Space) ......................... 151
Reset Sequence (Advanced Mode with On-Chip ROM Enabled).......................... 82
Stack Status after Exception Handling ................................................................... 86
Operation when SP Value Is Odd........................................................................... 87
Block Diagram of Interrupt Controller................................................................... 90
Block Diagram of Interrupts IRQ15 to IRQ0......................................................... 102
Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0 ................................................................................... 109
Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2 ................................................................................... 111
Interrupt Exception Handling................................................................................. 113
Contention between Interrupt Generation and Disabling ....................................... 116
Block Diagram of Bus Controller .......................................................................... 120
CS and Address Assertion Period Extension (Example of 3-State Access Space
and RDNn = 0) ....................................................................................................... 131
RAS Signal Assertion Timing (2-State Column Address Output Cycle,
Full Access)............................................................................................................ 139
Area Divisions........................................................................................................ 145
CSn Signal Output Timing (n = 0 to 7) .................................................................. 150
Access Sizes and Data Alignment Control (8-Bit Access Space) .......................... 151
Bus Timing for 8-Bit, 2-State Access Space .......................................................... 153

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