DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 176

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 5 Interrupt Controller
5.7
5.7.1
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
Rev.6.00 Mar. 18, 2009 Page 116 of 980
REJ09B0050-0600
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Usage Notes
Contention between Interrupt Generation and Disabling
φ
Figure 5.6 Contention between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
TCIV exception handling