DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 273

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

DMAS260A_010020020100
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
• Choice of short address mode or full address mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
• Module stop mode can be set
⎯ Short address mode
⎯ Full address mode
mode)
Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception
complete interrupt
A/D converter conversion end interrupt
External request
Auto-request
Maximum of 4 channels can be used
Dual address mode or single address mode can be selected
In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
In single address mode, transfer source or transfer destination address only is specified as
24 bits
In single address mode, transfer can be performed in one bus cycle
Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Maximum of 2 channels can be used
Transfer source and transfer destination addresses as specified as 24 bits
Choice of normal mode or block transfer mode
Features
Section 7 DMA Controller (DMAC)
Rev.6.00 Mar. 18, 2009 Page 213 of 980
Section 7 DMA Controller (DMAC)
REJ09B0050-0600