DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 767

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

8. The maximum number of repetitions of the program/program-verify sequence to the same bit
(N) must not be exceeded.
Note 7: Write Pulse Width
Note: Use a z3 µs write pulse for additional
Number of Writes (n)
Additional program data
storage area (128 bytes)
Reprogram data storage
Write pulse application subroutine
Wait (z1) μs or (z2) ms or (z3) μs
Program data storage
area (128 bytes)
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
Set PSU bit in FLMCR1
Write pulse application
Clear P bit in FLMCR1
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
Disable WDT
Enable WDT
Wait (y) μs
Wait (α) μs
Wait (β) μs
End sub
Figure 19.7 Program/Program-Verify Flowchart
Write Time (z) μs
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison between stored data in the program data area and verify data).
4. A 128-byte areas for storing program data, reprogram data, and additional program data must be provided in the RAM. The contents of the
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the programming operation. See Note *7 for the pulse widths.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 25.2.5, Flash Memory Characteristics.
Program Data Operation Chart
Additional Program Data Operation Chart
*6
*5 *6
Reprogram Data (X')
be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Programming is executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for which programming has been completed will
be subjected to additional programming if they fail the subsequent verify operation.
reprogram and additional program data are modified as programming proceeds.
When writing of additional-programming data is executed, a (z3) μs write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
Original Data (D)
0
1
0
1
Increment address
Verify Data (V)
Verify Data (V)
0
1
0
1
0
1
0
1
NG
Store 128-byte program data in program
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
Section 19 Flash Memory (0.35-μm F-ZTAT Version)
H'FF dummy write to verify address
Transfer additional program data to
Sequentially write 128-byte data in
data area and reprogram data area
Additional Program Data (Y)
additional program data area
Reprogram data computation
Clear SWE bit in FLMCR1
Reprogram Data (X)
Clear PV bit in FLMCR1
Set SWE bit in FLMCR1
(additional programming)
Set PV bit in FLMCR1
Start of programming
Write pulse application
Write pulse application
End of programming
Write data = verify
Read verify data
(z1) μs or (z2) μs
data verification
flash memory
Wait (x) μs
Wait (γ) μs
Wait (ε) μs
completed?
Wait (η) μs
Wait (θ) μs
data area
128-byte
1
0
1
0
1
6 ≥ n ?
6 ≥ n ?
m = 0?
m = 0
(z3) µs
n = 1
data?
Start
OK
OK
OK
OK
OK
Sub-routine-call
Subroutine-call
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
NG
NG
NG
Rev.6.00 Mar. 18, 2009 Page 707 of 980
NG
*6
*6
*4
*1
See Note 7 for pulse width
*6
*2
*3
*4
*6
*1
*6
*4
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
Clear SWE bit in FLMCR1
Comments
Comments
Programming failure
Wait (θ) μs
n ≥ (N)?
OK
*6
NG
n ← n + 1
*6
REJ09B0050-0600