DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 886

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 23 Power-Down Modes
23.1
The registers relating to the power-down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 22.1.1, System Clock Control Register (SCKCR).
• System clock control register (SCKCR)
• Standby control register (SBYCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
• Extension module stop control register H (EXMSTPCRH)
• Extension module stop control register L (EXMSTPCRL)
23.1.1
SBYCR performs software standby mode control.
Rev.6.00 Mar. 18, 2009 Page 826 of 980
REJ09B0050-0600
Bit
7
6
Bit Name
SSBY
OPE
Standby Control Register (SBYCR)
Register Descriptions
Initial Value
0
1
R/W
R/W
R/W
Description
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP
1: Shifts to software standby mode after the
This bit does not change when clearing the
software standby mode by using external
interrupts and shifting to normal operation. This bit
should be written 0 when clearing.
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS, LCAS) is retained or set to
the high-impedance state in software standby
mode.
0: In software standby mode, address bus and
1: In software standby mode, address bus and
instruction is executed
SLEEP instruction is executed
bus control signals are high-impedance
bus control signals retain output state