DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 34

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

13.5 Interrupts........................................................................................................................... 536
13.6 Usage Notes ...................................................................................................................... 536
Section 14 Serial Communication Interface (SCI, IrDA)
14.1 Features............................................................................................................................. 541
14.2 Input/Output Pins .............................................................................................................. 544
14.3 Register Descriptions ........................................................................................................ 545
14.4 Operation in Asynchronous Mode .................................................................................... 576
14.5 Multiprocessor Communication Function......................................................................... 588
14.6 Operation in Clocked Synchronous Mode ........................................................................ 595
Rev.6.00 Mar. 18, 2009 Page xxxii of lviii
REJ09B0050-0600
13.6.1 Notes on Register Access..................................................................................... 536
13.6.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 538
13.6.3 Changing Value of CKS2 to CKS0...................................................................... 538
13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 538
13.6.5 Internal Reset in Watchdog Timer Mode............................................................. 539
13.6.6 System Reset by WDTOVF Signal...................................................................... 539
14.3.1 Receive Shift Register (RSR) .............................................................................. 546
14.3.2 Receive Data Register (RDR) .............................................................................. 546
14.3.3 Transmit Data Register (TDR)............................................................................. 546
14.3.4 Transmit Shift Register (TSR) ............................................................................. 547
14.3.5 Serial Mode Register (SMR) ............................................................................... 547
14.3.6 Serial Control Register (SCR).............................................................................. 551
14.3.7 Serial Status Register (SSR) ................................................................................ 556
14.3.8 Smart Card Mode Register (SCMR).................................................................... 563
14.3.9 Bit Rate Register (BRR) ...................................................................................... 564
14.3.10 IrDA Control Register (IrCR) .............................................................................. 573
14.3.11 Serial Extension Mode Register (SEMR) ............................................................ 574
14.4.1 Data Transfer Format........................................................................................... 576
14.4.2 Receive Data Sampling Timing and Reception Margin in
14.4.3 Clock.................................................................................................................... 579
14.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 580
14.4.5 Data Transmission (Asynchronous Mode)........................................................... 581
14.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 584
14.5.1 Multiprocessor Serial Data Transmission ............................................................ 589
14.5.2 Multiprocessor Serial Data Reception ................................................................. 591
14.6.1 Clock.................................................................................................................... 595
14.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 596
14.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 597
14.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 600
Asynchronous Mode ............................................................................................ 578
........................................ 541