DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 711

MCU 3V 384K 128-QFP

DF2367VF33

Manufacturer Part Number
DF2367VF33
Description
MCU 3V 384K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2367VF33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VF33
HD64F2367VF33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2367VF33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls
4. The last byte data is read by reading ICDRR.
(master output)
(master output)
while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge
before reading ICDRR, to be returned to the master device, is reflected to the next transmit
frame.
(slave output)
(slave output)
processing
ICDRS
ICDRR
RDRF
User
SCL
SDA
SDA
SCL
Figure 15.11 Slave Receive Mode Operation Timing 1
[2] Read ICDRR (dummy read), and clear RDRF.
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 651 of 980
Bit 3
5
Bit 2
6
2
C Bus Interface2 (IIC2) (Option)
Bit 1
[2] Read ICDRR, and clear RDRF.
7
Bit 0
8
REJ09B0050-0600
A
9
Bit 7
Data 1
1
Data 2

Related parts for DF2367VF33