DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 425

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

9.8.1
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit
7
6
5
4
3
2
1
0
Bit Name
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
Port A Data Direction Register (PADDR)
Initial Value
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Description
•
Pins PA4 to PA0 are address outputs.
For pins PA6 and PA5, when the corresponding
A22E and A21E bits are set to 1, setting a PADDR
bit to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes the
pin an input port. Clearing A22E and A21E bits to 0
makes the corresponding port A pin an I/O port, and
its function can be switched with PADDR. For pin
PA7, when the A23E bit is set to 1, setting the
PA7DDR bit to 1 makes the pin an address output,
while clearing the bit to 0 makes the pin an input
port. When the CS7E bit is set to 1 while the A23E
bit is cleared to 0, pin PA7 functions as the CS7
output pin when PA7DDR is set to 1, and as an
input port when the bit is cleared to 0. When the
CS7E bit is cleared to 0, pin PA7 is an I/O port, and
its function can be switched with PA7DDR.
•
For pins PA6 to PA0, when the corresponding A22E
to A16E bits are set to 1, setting a PADDR bit to 1
makes the corresponding port A pin an address
output, while clearing the bit to 0 makes the pin an
input port. Clearing A22E to A21E bits to 0 makes
the corresponding port A pin an I/O port, and its
function can be switched with PADDR. For pin PA7,
when the A23E bit is set to 1, setting the PA7DDR
bit to 1 makes the pin an address output, while
clearing the bit to 0 makes the pin an input port.
When the CS7E bit is set to 1 while the A23E bit is
cleared to 0, pin PA7 functions as the CS7 output
pin when PA7DDR is set to 1, and as an input port
when the bit is cleared to 0. When the CS7E bit is
cleared to 0, pin PA7 is an I/O port, and its function
can be switched with PA7DDR.
•
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Modes 1 and 2
Modes 4 and 7 (when EXPE = 1)
Mode 7 (when EXPE = 0)
Rev.6.00 Mar. 18, 2009 Page 365 of 980
Section 9 I/O Ports
REJ09B0050-0600