DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 650

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 14 Serial Communication Interface (SCI, IrDA)
Rev.6.00 Mar. 18, 2009 Page 590 of 980
REJ09B0050-0600
Clear DR to 0 and set DDR to 1
Write transmit data to TDR and
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
Start of transmission
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Break output?
Initialization
TDRE = 1?
TEND = 1?
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
Note: * Not supported by the H8S/2366F.
[1]
[2]
[3]
[4]
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1,
a frame of 1s is output, and
transmission is enabled.
SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC* or DTC is activated by a
transmit-data-empty interrupt
(TXI) request, and data is written
to TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.