DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 231

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
to be inserted between the T
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the RAS signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.23 shows an example of the timing when one T
Read
Write
Note: n = 2, 3
Figure 6.23 Example of Timing with One Row Address Output Maintenance State
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
r
cycle, in which the RAS signal goes low, and the T
T
p
(RAST = 0, CAST = 0)
Row address
T
r
rw
states, in which row address output is maintained,
T
Rev.6.00 Mar. 18, 2009 Page 171 of 980
rw
Section 6 Bus Controller (BSC)
High
High
T
Column address
c1
rw
REJ09B0050-0600
c1
state is set.
cycle, in which
T
c2