MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet

no-image

MC68HC16Z1CFC16

Manufacturer Part Number
MC68HC16Z1CFC16
Description
IC MPU 1K RAM 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheets

Specifications of MC68HC16Z1CFC16

Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC16Z1CFC16
Manufacturer:
FREESCALE
Quantity:
1 410
Part Number:
MC68HC16Z1CFC16
Manufacturer:
FREESCALE
Quantity:
5 530
Part Number:
MC68HC16Z1CFC16
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC16Z1CFC16
Manufacturer:
MOTOROLA
Quantity:
1
Part Number:
MC68HC16Z1CFC16
Manufacturer:
FREESCALE
Quantity:
132
Part Number:
MC68HC16Z1CFC16
Manufacturer:
FREESCALE
Quantity:
132
Part Number:
MC68HC16Z1CFC16
Manufacturer:
MOT
Quantity:
1
© Freescale Semiconductor, Inc., 2004. All rights reserved.
HC16
Freescale Semiconductor
HC16
HC16
M68HC16Z Series
MC68CM16Z1
MC68HC16Z1
MC68HC16Z2
MC68HC16Z3
MC68HC16Z4
MC68CK16Z1
MC68CK16Z4
User’s Manual
Order this document by
MC68HC16ZUM/AD

MC68HC16Z1CFC16 Summary of contents

Page 1

... Freescale Semiconductor HC16 HC16 HC16 M68HC16Z Series © Freescale Semiconductor, Inc., 2004. All rights reserved. Order this document by MC68HC16ZUM/AD MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 MC68HC16Z3 MC68HC16Z4 MC68CK16Z4 User’s Manual ...

Page 2

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

Page 3

... Freescale Semiconductor, Inc. Paragraph 2.1 Symbols and Operators .............................................................................2-1 2.2 CPU16 Register Mnemonics .....................................................................2-2 2.3 Register Mnemonics ..................................................................................2-3 2.4 Conventions ..............................................................................................2-6 3.1 M68HC16 Z-Series MCU Features ...........................................................3-1 3.1.1 Central Processor Unit (CPU16/CPU16L) .........................................3-1 3.1.2 System Integration Module (SIM/SIML) ............................................3-1 3.1.3 Standby RAM (SRAM) ......................................................................3-1 3.1.4 Masked ROM Module (MRM) — ...

Page 4

... Freescale Semiconductor, Inc. Paragraph 4.2.7 Multiply and Accumulate Registers ...................................................4-5 4.3 Memory Management ...............................................................................4-5 4.3.1 Address Extension ............................................................................4-6 4.3.2 Extension Fields ................................................................................4-6 4.4 Data Types ................................................................................................4-6 4.5 Memory Organization ................................................................................4-7 4.6 Addressing Modes .....................................................................................4-8 4.6.1 Immediate Addressing Modes ...........................................................4-9 4.6.2 Extended Addressing Modes ..........................................................4-10 4 ...

Page 5

... Freescale Semiconductor, Inc. Paragraph 4.14.4 Background Debug Mode ................................................................4-42 4.14.4.1 Enabling BDM .........................................................................4-42 4.14.4.2 BDM Sources ..........................................................................4-42 4.14.4.3 Entering BDM ..........................................................................4-42 4.14.4.4 BDM Commands .....................................................................4-43 4.14.4.5 Returning from BDM ...............................................................4-43 4.14.4.6 BDM Serial Interface ...............................................................4-44 4.15 Recommended BDM Connection ............................................................4-45 4.16 Digital Signal Processing ...

Page 6

... Freescale Semiconductor, Inc. Paragraph 5.5.1.7 Function Codes .......................................................................5-32 5.5.1.8 Data Size Acknowledge Signals .............................................5-32 5.5.1.9 Bus Error Signal ......................................................................5-33 5.5.1.10 Halt Signal ...............................................................................5-33 5.5.1.11 Autovector Signal ....................................................................5-33 5.5.2 Dynamic Bus Sizing ........................................................................5-33 5.5.3 Operand Alignment .........................................................................5-35 5.5.4 Misaligned Operands ......................................................................5-35 5.5.5 Operand Transfer Cases ...

Page 7

... Freescale Semiconductor, Inc. Paragraph 5.8.1 Interrupt Exception Processing .......................................................5-58 5.8.2 Interrupt Priority and Recognition ....................................................5-58 5.8.3 Interrupt Acknowledge and Arbitration ............................................5-59 5.8.4 Interrupt Processing Summary ........................................................5-60 5.8.5 Interrupt Acknowledge Bus Cycles ..................................................5-61 5.9 Chip-Selects ............................................................................................5-61 5.9.1 Chip-Select Registers ......................................................................5-63 5.9.1.1 Chip-Select Pin Assignment Registers ...................................5-64 5 ...

Page 8

... Freescale Semiconductor, Inc. Paragraph ANALOG-TO-DIGITAL CONVERTER 8.1 General ......................................................................................................8-1 8.2 External Connections ................................................................................8-1 8.2.1 Analog Input Pins ..............................................................................8-2 8.2.2 Analog Reference Pins ......................................................................8-3 8.2.3 Analog Supply Pins ...........................................................................8-3 8.3 Programmer’s Model .................................................................................8-3 8.4 ADC Bus Interface Unit .............................................................................8-3 8.5 Special Operating Modes ..........................................................................8-3 8 ...

Page 9

... Freescale Semiconductor, Inc. Paragraph 9.1 General ......................................................................................................9-1 9.2 QSM Registers and Address Map .............................................................9-2 9.2.1 QSM Global Registers .......................................................................9-2 9.2.1.1 Low-Power Stop Mode Operation .............................................9-2 9.2.1.2 Freeze Operation ......................................................................9-3 9.2.1.3 QSM Interrupts ..........................................................................9-3 9.2.2 QSM Pin Control Registers ...............................................................9-4 9.3 Queued Serial Peripheral Interface ...........................................................9-5 9 ...

Page 10

... Freescale Semiconductor, Inc. Paragraph MULTICHANNEL COMMUNICATION INTERFACE 10.1 General ....................................................................................................10-1 10.2 MCCI Registers and Address Map ..........................................................10-2 10.2.1 MCCI Global Registers ....................................................................10-2 10.2.1.1 Low-Power Stop Mode ............................................................10-2 10.2.1.2 Privilege Levels .......................................................................10-3 10.2.1.3 MCCI Interrupts .......................................................................10-3 10.2.2 Pin Control and General-Purpose I/O .............................................10-4 10 ...

Page 11

... Freescale Semiconductor, Inc. Paragraph 10.4.5.7 Idle-Line Detection ................................................................10-21 10.4.5.8 Receiver Wake-Up ................................................................10-22 10.4.5.9 Internal Loop .........................................................................10-22 10.5 MCCI Initialization .................................................................................10-23 GENERAL-PURPOSE TIMER 11.1 General ....................................................................................................11-1 11.2 GPT Registers and Address Map ............................................................11-2 11.3 Special Modes of Operation ....................................................................11-3 11.3.1 Low-Power Stop Mode ....................................................................11-3 11 ...

Page 12

... Freescale Semiconductor, Inc. Paragraph ELECTRICAL CHARACTERISTICS MECHANICAL DATA AND ORDERING INFORMATION B.1 Obtaining Updated M68HC16 Z-Series MCU Mechanical Information .... B-8 B.2 Ordering Information ................................................................................ B-8 C.1 M68MMDS1632 Modular Development System ...................................... C-1 C.2 M68MEVB1632 Modular Evaluation Board .............................................. C-2 D.1 Central Processing Unit ............................................................................ D-1 D ...

Page 13

... Freescale Semiconductor, Inc. Paragraph D.2.22 Master Shift Registers .................................................................... D-22 D.2.23 Test Module Shift Count Register .................................................. D-22 D.2.24 Test Module Repetition Count Register ......................................... D-22 D.2.25 Test Module Control Register ......................................................... D-22 D.2.26 Test Module Distributed Register ................................................... D-22 D.3 Standby RAM Module ............................................................................ D-23 D.3.1 RAM Module Configuration Register ...

Page 14

... Freescale Semiconductor, Inc. Paragraph D.7.1 MCCI Module Configuration Register ............................................. D-54 D.7.2 MCCI Test Register ........................................................................ D-55 D.7.3 SCI Interrupt Level Register/MCCI Interrupt Vector Register ......... D-55 D.7.4 MCCI Interrupt Vector Register ...................................................... D-56 D.7.5 SPI Interrupt Level Register ........................................................... D-56 D.7.6 MCCI Pin Assignment Register ...................................................... D-57 D ...

Page 15

... Freescale Semiconductor, Inc. Paragraph E.1.5 INITRAM.ASM ................................................................................ E-11 E.1.6 INITSCI.ASM .................................................................................. E-12 E.2 Programming Examples ......................................................................... E-12 E.2.1 SIM Programming Examples .......................................................... E-13 E.2.1.1 Example 1 - Using Ports E and F ........................................... E-13 E.2.1.2 Example 2 - Using Chip-Selects ............................................ E-14 E.2.1.3 Example 3 - Changing Clock Frequencies ............................. E-16 E.2.1.4 Example 4 - Software Watchdog, Periodic Interrupt, and Autovector Demo ...

Page 16

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 17

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 3-1 MC68HC16Z1/CK16Z1/CM16Z1 Block Diagram ........................................... 3-4 3-2 MC68HC16Z2/Z3 Block Diagram ................................................................... 3-5 3-3 MC68HC16Z4/CK16Z4 Block Diagram .......................................................... 3-6 3-4 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package ....................................................................................... 3-7 3-5 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 144-Pin Package ....................................................................................... 3-8 3-6 MC68HC16Z4/CKZ4 Pin Assignments for 132-Pin Package ......................... 3-9 3-7 MC68HC16Z4/CKZ4 Pin Assignments for 144-Pin Package ...

Page 18

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 5-12 Word Read Cycle Flowchart ......................................................................... 5-38 5-13 Write Cycle Flowchart .................................................................................. 5-39 5-14 CPU Space Address Encoding .................................................................... 5-41 5-15 Breakpoint Operation Flowchart ................................................................... 5-42 5-16 LPSTOP Interrupt Mask Level ...................................................................... 5-43 5-17 Bus Arbitration Flowchart for Single Request ............................................... 5-47 5-18 Preferred Circuit for Data Bus Mode Select Conditioning ...

Page 19

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 10-6 SCI Receiver Block Diagram ...................................................................... 10-15 11-1 GPT Block Diagram ...................................................................................... 11-2 11-2 Prescaler Block Diagram .............................................................................. 11-9 11-3 Capture/Compare Unit Block Diagram ....................................................... 11-11 11-4 Input Capture Timing Example ................................................................... 11-13 11-5 Pulse Accumulator Block Diagram ............................................................. 11-15 11-6 PWM Block Diagram ...

Page 20

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure A-33 Force Compare (CLEAR) .............................................................................A-61 A-34 Low Voltage 8-Bit ADC Conversion Accuracy ..............................................A-68 A-35 8-Bit ADC Conversion Accuracy ..................................................................A-69 A-36 Low Voltage 10-Bit ADC Conversion Accuracy ............................................A-70 A-37 10-Bit ADC Conversion Accuracy ................................................................A-71 B-1 MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 Pin Assignments for 132-Pin Package ...

Page 21

... Freescale Semiconductor, Inc. Table 1-1 M68HC16 Z-Series MCUs............................................................................... 1-1 1-2 Z-Series MCU Reference Frequencies ........................................................... 1-2 3-1 M68HC16 Z-Series Pin Characteristics......................................................... 3-11 3-2 M68HC16 Z-Series Driver Types .................................................................. 3-12 3-3 M68HC16 Z-Series Power Connections ....................................................... 3-13 3-4 M68HC16 Z-Series Signal Characteristics .................................................... 3-13 3-5 M68HC16 Z-Series Signal Function.............................................................. 3-15 4-1 Addressing Modes ...

Page 22

... Freescale Semiconductor, Inc. Table 5-25 Chip-Select Base and Option Register Reset Values ................................... 5-69 5-26 CSBOOT Base and Option Register Reset Values....................................... 5-70 6-1 SRAM Configuration........................................................................................ 6-1 6-2 SRAM Array Address Space Type .................................................................. 6-2 7-1 ROM Array Space Field .................................................................................. 7-2 7-2 Wait States Field ............................................................................................. 7-3 8-1 FRZ Field Selection ...

Page 23

... Freescale Semiconductor, Inc. Table A-3 Typical Ratings, 5V, 16.78-MHz Operation .....................................................A-3 A-4 Typical Ratings, 20.97-MHz Operation ...........................................................A-3 A-5 Typical Ratings, 25.17-MHz ............................................................................A-4 A-6 Thermal Characteristics ..................................................................................A-5 A-7 Low Voltage Clock Control Timing ..................................................................A-6 A-8 16.78-MHz Clock Control Timing ....................................................................A-7 A-9 20.97-MHz Clock Control Timing ....................................................................A-8 A-10 25 ...

Page 24

... Freescale Semiconductor, Inc. Table D-3 Show Cycle Enable Bits ..................................................................................D-6 D-4 Port E Pin Assignments.................................................................................D-10 D-5 Port F Pin Assignments.................................................................................D-11 D-6 Software Watchdog Divide Ratio...................................................................D-12 D-7 Bus Monitor Time-Out Period........................................................................D-13 D-8 Pin Assignment Field Encoding.....................................................................D-16 D-9 CSPAR0 Pin Assignments ............................................................................D-16 D-10 CSPAR1 Pin Assignments ...

Page 25

... Freescale Semiconductor, Inc. Table D-44 PAMOD and PEDGE Effects.........................................................................D-71 D-45 PACLK[1:0] Effects........................................................................................D-71 D-46 OM/OL[5:2] Effects........................................................................................D-72 D-47 EDGE[4:1] Effects .........................................................................................D-72 D-48 CPR[2:0]/Prescaler Select Field....................................................................D-73 D-49 PPR[2:0] Field ...............................................................................................D-75 D-50 PWM Frequency Ranges ..............................................................................D-76 M68HC16 Z SERIES USER’S MANUAL ...

Page 26

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 27

... Freescale Semiconductor, Inc. M68HC16 Z-series microcontrollers (including the MC68HC16Z1, MC68CM16Z1, MC68CK16Z1, MC68HC16Z2, MC68HC16Z3, MC68HC16Z4, and MC68CK16Z4) are high-speed 16-bit control units that are upwardly code compatible with M68HC11 controllers. All are members of the M68HC16 Family of modular microcontrollers. M68HC16 microcontroller units (MCUs) are built from standard modules that interface via a common internal bus ...

Page 28

... Freescale Semiconductor, Inc. Table 1-2 Z-Series MCU Reference Frequencies MCU MC68HC16Z1 MC68CM16Z1 MC68CK16Z1 MC68HC16Z2 MC68HC16Z3 MC68HC16Z4 MC68CK16Z4 NOTES: 1. The nominal slow reference frequency is 32.768 kHz, but can range from kHz. The nominal fast reference frequency is 4.194 MHz, but can range from 1MHz to 6.25 MHz. ...

Page 29

... Freescale Semiconductor, Inc. The following tables show the nomenclature used throughout the M68HC16 Z-series manual. 2.1 Symbols and Operators Symbol - * / • NOT : « M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, SECTION 2 NOMENCLATURE Function Addition Subtraction (two’s complement) or negation ...

Page 30

... Freescale Semiconductor, Inc. 2.2 CPU16 Register Mnemonics Mnemonic CCR XMSK YMSK 2-2 For More Information On This Product, Register Accumulator A Accumulator M Accumulator B Condition code register Accumulator D Accumulator E Extended addressing extension field MAC multiplier register MAC multiplicand register Index register X Index register Y Index register Z ...

Page 31

... Freescale Semiconductor, Inc. 2.3 Register Mnemonics Mnemonic ADCMCR ADCTEST ADCTL[0:1] ADCSTAT CFORC CREG CR[0:F] CSBARBT CSBAR[0:10] CSORBT CSOR[0:10] CSPAR[0:1] DDRE DDRF DDRGP DDRM DDRQS DREG GPTMCR GPTMTR ICR ILSCI ILSPI LJSRR[0:7] LJURR[0:7] MIVR MMCR MPAR MRMCR MTEST OC1D OC1M PACNT PACTL ...

Page 32

... Freescale Semiconductor, Inc. Mnemonic PICR PITR PORTADA PORTC PORTE PORTF PORTGP PORTMC PORTMCP PORTQS PQSPAR PRESCL PWMA PWMB PWMBUFA PWMBUFB PWMC PWMCNT QILR QIVR QSMCR QTEST RAMBAH RAMBAL RAMMCR RAMTST RJURR[0:7] ROMBAH ROMBAL ROMBS[0:3] RR[0:F] RSR SCCR[0:1] SCCR0[A:B] SCCR1[A:B] SCDR SCDR[A:B] ...

Page 33

... Freescale Semiconductor, Inc. Mnemonic SCSR SCSR[A:B] SIGHI SIGLO SIMCR SIMTR SIMTRE SPCR SPCR[0:3] SPDR SPSR SPSR SWSR SYNCR SYPCR TCNT TCTL[1:2] TFLG[1:2] TI4/O5 TIC[1:3] TMSK[1:2] TOC[1:4] TR[0:F] TSTMSRA TSTMSRB TSTRC TSTSC M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, ...

Page 34

... Freescale Semiconductor, Inc. 2.4 Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a bit or bits. Clear refers specifically to establishing logic level zero on a bit or bits. ...

Page 35

... Freescale Semiconductor, Inc. This section provides general information on M68HC16 Z-series MCUs. It lists fea- tures of each of the modules, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontrol- ler and for individual modules are provided in TERISTICS ...

Page 36

... Freescale Semiconductor, Inc. 3.1.4 Masked ROM Module (MRM) — (MC68HC16Z2/Z3 Only) • 8-Kbyte array, accessible as bytes or words • User-selectable default base address • User-selectable bootstrap ROM function • User-selectable ROM verification code 3.1.5 Analog-to-Digital Converter (ADC) • Eight channels, eight result registers • ...

Page 37

... Freescale Semiconductor, Inc. M68HC16 Z-series microcontrollers are available in both 132- and 144-pin packages. Figure 3-4 shows an MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 pin assignment drawing based on a 132-pin plastic surface-mount package. MC68HC16Z1/CKZ1/CMZ1/Z2/Z3 pin assignment drawing based on a 144-pin plastic surface-mount package. Figure 3-6 drawing based on a 132-pin plastic surface-mount package. ...

Page 38

... Freescale Semiconductor, Inc. PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 IC4/OC5/OC1 OC4/OC1/PGP6 OC4/OC1 OC3/OC1/PGP5 OC3/OC1 OC2/OC1/PGP4 OC2/OC1 OC1/PGP3 OC1 IC3/PGP2 IC3 IC2/PGP1 IC2 IC1/PGP0 IC1 RXD TXD/PQS7 TXD PCS3/PQS6 PCS3 PCS2/PQS5 PCS2 PCS1/PQS4 PCS1 PCS0/SS/PQS3 PCS0 SCK/PQS2 SCK MOSI/PQS1 MOSI MISO/PQS0 MISO V DD ...

Page 39

... Freescale Semiconductor, Inc. PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 IC4/OC5/OC1 OC4/OC1/PGP6 OC4/OC1 OC3/OC1/PGP5 OC3/OC1 OC2/OC1/PGP4 OC2/OC1 OC1/PGP3 OC1 IC3/PGP2 IC3 IC2/PGP1 IC2 IC1/PGP0 IC1 RXD TXD/PQS7 TXD PCS3/PQS6 PCS3 PCS2/PQS5 PCS2 PCS1/PQS4 PCS1 PCS0/SS/PQS3 PCS0 SCK/PQS2 SCK MOSI/PQS1 MOSI MISO/PQS0 MISO V DD ...

Page 40

... Freescale Semiconductor, Inc. PWMA PWMB PCLK PAI IC4/OC5/OC1/PGP7 IC4/OC5/OC1 OC4/OC1/PGP6 OC4/OC1 OC3/OC1/PGP5 OC3/OC1 OC2/OC1/PGP4 OC2/OC1 OC1/PGP3 OC1 IC3/PGP2 IC3 IC2/PGP1 IC2 IC1/PGP0 IC1 TXDA/PMC7 TXDA RXDA/PMC6 RXDA TXDB/PMC5 TXDB RXDB/PMC4 RXDB SS/PMC3 SS SCK/PMC2 SCK MOSI/PMC1 MOSI MISO/PMC0 MISO DDA V SSA AN7/PADA7 ...

Page 41

... Freescale Semiconductor, Inc. TXD/PQS7 18 ADDR1 19 ADDR2 20 VDD 21 VSS 22 ADDR3 23 ADDR4 24 ADDR5 25 ADDR6 26 ADDR7 27 ADDR8 28 VSS 29 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12 33 ADDR13 34 ADDR14 35 ADDR15 36 ADDR16 37 ADDR17 38 ADDR18 39 VDD 40 VSS 41 VDDA 42 VSSA 43 AN0/PADA0 44 AN1/PADA1 45 AN2/PADA2 46 AN3/PADA3 47 AN4/PADA4 48 AN5/PADA5 49 VRH 50 NOTES: 1. MMMMM = MASK OPTION NUMBER 2 ...

Page 42

... Freescale Semiconductor, Inc. VDD 109 AS/PE5 110 DS/PE4 111 AVEC/PE2 112 DSACK1/PE1 113 DSACK0/PE0 114 ADDR0 115 DATA15 116 DATA14 117 DATA13 118 DATA12 119 DATA11 120 DATA10 121 VSS 122 NC 123 VDD 124 DATA9 125 DATA8 126 DATA7 127 DATA6 ...

Page 43

... Freescale Semiconductor, Inc. TXDA/PMC7 18 ADDR1 19 ADDR2 20 VDD 21 VSS 22 ADDR3 23 ADDR4 24 ADDR5 25 ADDR6 26 ADDR7 27 ADDR8 28 VSS 29 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12 33 ADDR13 34 ADDR14 35 ADDR15 36 ADDR16 37 ADDR17 38 ADDR18 39 VDD 40 VSS 41 VDDA 42 VSSA 43 AN0/PADA0 44 AN1/PADA1 45 AN2/PADA2 46 AN3/PADA3 47 AN4/PADA4 48 AN5/PADA5 49 VRH 50 NOTES: 1. MMMMM = MASK OPTION NUMBER 2 ...

Page 44

... Freescale Semiconductor, Inc. VDD 109 AS/PE5 110 DS/PE4 111 AVEC/PE2 112 DSACK1/PE1 113 DSACK0/PE0 114 ADDR0 115 DATA15 116 DATA14 117 DATA13 118 DATA12 119 DATA11 120 DATA10 121 VSS 122 NC 123 VDD 124 DATA9 125 DATA8 126 DATA7 127 DATA6 ...

Page 45

... Freescale Semiconductor, Inc. 3.4 Pin Descriptions The following tables are a summary of the functional characteristics of M68HC16 Z- series MCU pins. Table 3-1 use CMOS logic levels. An entry in the “Discrete I/O” column indicates that a pin can also be used for general-purpose input, output, or both. The I/O port designation is giv- en when it applies ...

Page 46

... Freescale Semiconductor, Inc. Table 3-1 M68HC16 Z-Series Pin Characteristics (Continued) Pin Output Mnemonic Driver 4 — PCLK PCS0/SS Bo PCS[3: PWMA, PWMB R/W A RESET Bo RXD — RXDA 3 Bo RXDB 3 Bo SCK SCK Bo SIZ[1: TSC — TXD TXDA 3 Bo TXDB 2 — XFC 2 — XTAL NOTES: 1 ...

Page 47

... Freescale Semiconductor, Inc. Table 3-3 M68HC16 Z-Series Power Connections Pin Mnemonic V STBY V DDSYN V /V DDA SSA 3.5 Signal Descriptions The following tables define the M68HC16 Z-series MCU signals. nal origin, type, and active state. sorted alphabetically by mnemonic. MCU pins often have multiple functions. More than one description can apply to a pin ...

Page 48

... Freescale Semiconductor, Inc. Table 3-4 M68HC16 Z-Series Signal Characteristics (Continued) Signal Name MISO 1 MISO MODCLK MOSI 1 MOSI OC[5:1] PADA[7:0] PAI PC[6:0] PE[7:0] PF[7:0] PGP[7:0] PQS[7:0] PCLK PCS[3:0] PWMA, PWMB 1 PMC[7:0] QUOT R/W RESET RXD 1 RXDA 1 RXDB SCK 1 SCK SIZ[1: TSC TXD ...

Page 49

... Freescale Semiconductor, Inc. Table 3-5 M68HC16 Z-Series Signal Function Mnemonic Signal Name ADDR[19:0] Address Bus AN[7:0] ADC Analog Input AS Address Strobe AVEC Autovector BERR Bus Error BG Bus Grant Bus Grant BGACK Acknowledge BKPT Breakpoint BR Bus Request CLKOUT System Clockout CS[10:0] Chip-Selects ...

Page 50

... Freescale Semiconductor, Inc. Table 3-5 M68HC16 Z-Series Signal Function (Continued) Mnemonic Signal Name PF[7:0] Port F PGP[7:0] Port GP PQS[7:0] Port QS PWMA, PWMB Pulse Width Modulation QUOT Quotient Out R/W Read/Write RESET Reset RXD Receive Data (SCI) 1 SCI A Receive Data RXDA 1 SCI B Receive Data ...

Page 51

... Freescale Semiconductor, Inc. $000000 $YFF700 64 BYTES $YFF73F $YFF900 64 BYTES $YFF93F $YFFA00 128 BYTES $YFFA7F $YFFB00 SRAM CONTROL 8 BYTES $YFFB07 $YFFC00 512 BYTES $YFFDFF $FFFFFF Figure 3-8 MC68HC16Z1/CKZ1/CMZ1 Address Map M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, ADC GPT ...

Page 52

... Freescale Semiconductor, Inc. $000000 $YFF700 64 BYTES $YFF73F $YFF820 ROM CONTROL 32 BYTES $YFF83F $YFF900 64 BYTES $YFF93F $YFFA00 128 BYTES $YFFA7F $YFFB00 SRAM CONTROL 8 BYTES $YFFB07 $YFFC00 512 BYTES $YFFDFF $FFFFFF Figure 3-9 MC68HC16Z2/Z3 Address Map $000000 $YFF700 64 BYTES $YFF73F $YFF900 64 BYTES $YFF93F ...

Page 53

... Freescale Semiconductor, Inc. 3.7 Address Space Maps Figures 3-11 through 3-16 Address space can be split into physically distinct program and data spaces by decod- ing the MCU function code outputs. Figures 3-11, 3-12, and 3-13 program and data spaces. MCU function code outputs are decoded. ...

Page 54

... Freescale Semiconductor, Inc. $000000 BANK 0 RESET AND EXCEPTION VECTORS $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM $070000 AND DATA BANK 7 SPACE $07FFFF $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 $FA0000 BANK 10 $FB0000 ...

Page 55

... Freescale Semiconductor, Inc. $000000 BANK 0 RESET AND EXCEPTION VECTORS $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM $070000 AND DATA BANK 7 SPACE $07FFFF $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 $FA0000 BANK 10 $FB0000 ...

Page 56

... Freescale Semiconductor, Inc. $000000 BANK 0 RESET AND EXCEPTION VECTORS $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM $070000 AND DATA BANK 7 SPACE $07FFFF $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 $FA0000 BANK 10 $FB0000 ...

Page 57

... Freescale Semiconductor, Inc. $000000 BANK 0 $000008 $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM SPACE $070000 BANK 7 $07FFFF $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 $FA0000 BANK 10 $FB0000 BANK 11 512 KBYTE $FC0000 BANK 12 ...

Page 58

... Freescale Semiconductor, Inc. $000000 BANK 0 $000008 $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM SPACE $070000 BANK 7 $07FFFF $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 $FA0000 BANK 10 $FB0000 BANK 11 512 KBYTE $FC0000 BANK 12 ...

Page 59

... Freescale Semiconductor, Inc. $000000 BANK 0 $000008 $010000 BANK 1 $020000 BANK 2 $030000 BANK 3 512 KBYTE $040000 BANK 4 $050000 BANK 5 $060000 BANK 6 PROGRAM SPACE $070000 BANK 7 $07FFFF $080000 UNDEFINED 1 UNDEFINED $F7FFFF $F80000 BANK 8 $F90000 BANK 9 $FA0000 BANK 10 $FB0000 BANK 11 512 KBYTE $FC0000 BANK 12 ...

Page 60

... Freescale Semiconductor, Inc. 3-26 For More Information On This Product, OVERVIEW Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 61

... Freescale Semiconductor, Inc. CENTRAL PROCESSOR UNIT This section is an overview of the central processor unit (CPU16). For detailed infor- mation, refer to the CPU16 Reference Manual (CPU16RM/AD). 4.1 General The CPU16 provides compatibility with the M68HC11 CPU and also provides addition- al capabilities associated with 16- and 32-bit data sizes, 20-bit addressing, and digital signal processing ...

Page 62

... Freescale Semiconductor, Inc Figure 4-1 CPU16 Register Model 4-2 For More Information On This Product BIT POSITION A B ACCUMULATORS A AND B D ACCUMULATOR D (A:B) E ACCUMULATOR E IX INDEX REGISTER X IY INDEX REGISTER Y IZ INDEX REGISTER Z SP STACK POINTER SP PC PROGRAM COUNTER PC CONDITION CODE REGISTER CCR ...

Page 63

... Freescale Semiconductor, Inc. 4.2.1 Accumulators The CPU16 has two 8-bit accumulators (A and B) and one 16-bit accumulator (E). In addition, accumulators A and B can be concatenated into a second 16-bit double ac- cumulator (D). Accumulators A, B, and D are general-purpose registers that hold operands and re- sults during mathematical and data manipulation operations. ...

Page 64

... Freescale Semiconductor, Inc. 4.2.5 Condition Code Register The 16-bit condition code register is composed of two functional blocks. The eight MSB, which correspond to the CCR on the M68HC11, contain the low-power stop con- trol bit and processor status flags. The eight LSB contain the interrupt priority field, the DSP saturation mode control bit, and the program counter address extension field ...

Page 65

... Freescale Semiconductor, Inc. SM — Saturate Mode Bit When SM is set and either set, data read from AM using TMER or TMET is given maximum positive or negative value, depending on the state of the AM sign bit before overflow. PK[3:0] — Program Counter Address Extension Field This field is concatenated with the program counter to form a 20-bit address. ...

Page 66

... Freescale Semiconductor, Inc. 4.3.1 Address Extension All CPU16 resources used to generate addresses are effectively 20 bits wide. These resources include the index registers, program counter, and stack pointer. All address- ing modes use 20-bit addresses. Twenty-bit addresses are formed from a 16-bit byte address generated by an individ- ual CPU16 register and a 4-bit address extension contained in an associated exten- sion field ...

Page 67

... Freescale Semiconductor, Inc. Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit. Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and 30. There are 31 bits of magnitude, but use of the extension bits allows representation of numbers in the range – ...

Page 68

... Freescale Semiconductor, Inc. Address BIT BIT BIT BIT $0000 $0002 $0004 X OFFSET $0006 BCD1 $0008 $000A $000C $000E $0010 $0012 $0014 (Radix Point) $0016 (Radix Point) $0018 (Radix Point) $001A $001C (Radix Point) $001E « « « « 4-Bit Address Extension Figure 4-3 Data Types and Memory Organization 4 ...

Page 69

... Freescale Semiconductor, Inc. Table 4-1 Addressing Modes Mode Accumulator Offset Extended Immediate Indexed 8-Bit Indexed 16-Bit Indexed 20-Bit Inherent Post-Modified Index Relative All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an operand or an extension field to form a 20-bit effective address. Access across 64-Kbyte address boundaries is transparent. AD- DR[19:16] of the effective address are changed to make an access across a bank boundary ...

Page 70

... Freescale Semiconductor, Inc. 4.6.2 Extended Addressing Modes Regular extended mode instructions contain ADDR[15:0] in the word following the op- code. The effective address is formed by concatenating the EK field and the 16-bit byte address. EXT20 mode is used only by the JMP and JSR instructions. These instruc- tions contain a 20-bit effective address that is zero-extended to 24 bits to give the in- struction an even number of bytes ...

Page 71

... Freescale Semiconductor, Inc. 4.6.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode In M68HC11 systems, the direct addressing mode can be used to perform rapid ac- cesses to RAM or I/O mapped from $0000 to $00FF. The CPU16 uses the first 512 bytes of bank 0 for exception vectors. To provide an enhanced replacement for the M68HC11’ ...

Page 72

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary Mnemonic Operation Description ABA Add ABX Add (XK : IX) (000 : B) ABY Add (YK : IY) + (000 : B) ABZ Add (ZK : IZ) (000 : B) ACE Add (AM[31:16]) ACED Add (AM ADCA Add with Carry to A (A) (M) ADCB Add with Carry to B (B) ...

Page 73

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ADDB Add to B (B) ADDD Add ADDE Add ADE Add (E) + (D) ADX Add ADY Add ADZ Add AEX Add AEY Add AEZ Add AIS Add Immediate Data (SK SP) ...

Page 74

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ANDB AND B (B) (M) ANDD AND D ( ANDE AND E ( AND CCR (CCR) IMM16 1 ANDP ASL Arithmetic Shift Left ASLA Arithmetic Shift Left A ASLB Arithmetic Shift Left B ASLD Arithmetic Shift Left D ASLE ...

Page 75

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ASRA Arithmetic Shift Right A ASRB Arithmetic Shift Right B ASRD Arithmetic Shift Right D ASRE Arithmetic Shift Right E ASRM Arithmetic Shift Right AM ASRW Arithmetic Shift Right Word 2 Branch if Carry Clear branch ...

Page 76

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description BITB Bit Test B (B) (M) 2 Branch if Less Than BLE Equal to Zero 2 Branch if Lower branch BLS Same 2 Branch if Less Than branch BLT Zero 2 Branch if Minus branch BMI 2 Branch if Not Equal ...

Page 77

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description BSR Branch to Subroutine ( Push (PC) ( Push (CCR) ( (PK : PC) Offset 2 Branch if Overflow branch BVC Clear 2 Branch if Overflow Set branch BVS CBA Compare (A) CLR Clear a Byte in $00 Memory CLRA ...

Page 78

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description CPD Compare D to Memory ( CPE Compare E to Memory ( CPS Compare Stack (SP Pointer to Memory CPX Compare IX to (IX Memory CPY Compare IY to (IY Memory CPZ Compare IZ to (IZ Memory DAA Decimal Adjust A (A) ...

Page 79

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description EDIVS Extended Signed ( (IX) Integer Divide Quotient Remainder EMUL Extended Unsigned (E) (D) Multiply EMULS Extended Signed (E) (D) Multiply EORA Exclusive OR A (A) EORB Exclusive OR B (B) EORD Exclusive EORE Exclusive OR E (E) ...

Page 80

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description JMP Jump ea JSR Jump to Subroutine Push (PC) (SK SP) $0002 Push (CCR) (SK SP) $0002 ea Long Branch if Carry branch 2 LBCC Clear 2 Long Branch if Carry branch LBCS Set 2 Long Branch if Equal branch LBEQ ...

Page 81

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description LDAB Load B (M) LDD Load LDE Load LDED Load Concatenated ( and LDHI Initialize H and LDS Load LDX Load LDY Load LDZ Load M68HC16 Z SERIES USER’S MANUAL For More Information On This Product, ...

Page 82

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description LPSTOP Low Power Stop then STOP else NOP LSR Logical Shift Right LSRA Logical Shift Right A LSRB Logical Shift Right B LSRD Logical Shift Right D LSRE Logical Shift Right E LSRW ...

Page 83

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description ORAA OR A (A) ORAB OR B (B) ORD ORE Condition Code (CCR) IMM16 ORP Register PSHA Push A (SK : SP) + $0001 Push (A) (SK : SP) $0002 PSHB Push B (SK : SP) + $0001 Push (B) (SK : SP) $0002 PSHM ...

Page 84

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description Pull Multiple Registers For mask bits PULM Mask bits: If mask bit set 0 = CCR[15:4] ( Pull register (Reserved) PULMAC Pull MAC State Stack MAC Registers RMAC Repeating Repeat until (E) Multiply and ...

Page 85

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description RORW Rotate Right Word 3 Return from Interrupt (SK SP RTI Pull CCR (SK SP Pull PC (PK PC) Return from Subrou- ( RTS tine Pull PK ( Pull PC (PK : PC) SBA Subtract B from A (A) SBCA ...

Page 86

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description STAB Store B (B) STD Store D (D) STE Store E (E) STED Store Concatenated (E) D and E (D) M STS Store Stack Pointer (SP) STX Store IX (IX) STY Store IY (IY) STZ Store Z (IZ) SUBA ...

Page 87

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description SUBB Subtract from B (B) SUBD Subtract from D ( SUBE Subtract from E ( SWI Software Interrupt (PK PC) + $0002 Push (PC) (SK SP) $0002 Push (CCR) (SK SP) $0002 $0 SWI Vector SXT Sign Extend B into then $FF ...

Page 88

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description TMET Transfer Truncated If (SM ( then Saturation Value else AM[31:16] TMXED Transfer AM to AM[35:32 AM35 AM[31:16] AM[15:0] TPA Transfer CCR to A (CCR[15:8]) TPD Transfer CCR to D (CCR) TSKB Transfer (SK) ...

Page 89

... Freescale Semiconductor, Inc. Table 4-2 Instruction Set Summary (Continued) Mnemonic Operation Description XGDY Exchange D with IY (D) XGDZ Exchange D with IZ (D) XGEX Exchange E with IX (E) XGEY Exchange E with IY (E) XGEZ Exchange E with IZ (E) NOTES: 1. CCR[15:4] change according to the results of the operation. The PK field is not affected. ...

Page 90

... Freescale Semiconductor, Inc. Table 4-3 Instruction Set Abbreviations and Symbols A — Accumulator A AM — Accumulator M B — Accumulator B CCR — Condition code register D — Accumulator D E — Accumulator E EK — Extended addressing extension field IR — MAC multiplicand register HR — MAC multiplier register IX — ...

Page 91

... Freescale Semiconductor, Inc. 4.8 Comparison of CPU16 and M68HC11 CPU Instruction Sets Most M68HC11 CPU instructions are a source-code compatible subset of the CPU16 instruction set. However, certain M68HC11 CPU instructions have been replaced by functionally equivalent CPU16 instructions, and some CPU16 instructions with the same mnemonics as M68HC11 CPU instructions operate differently ...

Page 92

... Freescale Semiconductor, Inc. Table 4-4 CPU16 Implementation of M68HC11 CPU Instructions M68HC11 Instruction BHS BCC only BLO BCS only BSR Generates a different stack frame CLC Replaced by ANDP CLI Replaced by ANDP CLV Replaced by ANDP DES Replaced by AIS DEX Replaced by AIX DEY Replaced by AIY ...

Page 93

... Freescale Semiconductor, Inc. 4.9 Instruction Format CPU16 instructions consist of an 8-bit opcode that can be preceded by an 8-bit prebyte and followed by one or more operands. Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone. Page 1, 2, and 3 opcodes are pointed prebyte code on page 0. The prebytes are $17 (page 1), $27 (page 2), and $37 (page 3) ...

Page 94

... Freescale Semiconductor, Inc. 8-Bit Opcode with 8-Bit Operand Opcode 8-Bit Opcode with 4-Bit Index Extensions Opcode 8-Bit Opcode, Argument( Opcode 8-Bit Opcode with 8-Bit Prebyte, No Argument Prebyte 8-Bit Opcode with 8-Bit Prebyte, Argument( Prebyte 8-Bit Opcode with 20-Bit Argument Opcode Figure 4-4 Basic Instruction Formats 4 ...

Page 95

... Freescale Semiconductor, Inc. IPIPE0 IPIPE1 DATA A BUS Figure 4-5 Instruction Execution Model 4.10.1 Microsequencer The microsequencer controls the order in which instructions are fetched, advanced through the pipeline, and executed. It increments the program counter and generates multiplexed external tracking signals IPIPE0 and IPIPE1 from internal signals that con- trol execution sequence ...

Page 96

... Freescale Semiconductor, Inc. 4.11 Execution Process Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are evaluated in stage B. The execution unit can access operands in either stage A or stage B (stage B accesses are limited to 8-bit operands). When execution is complete, opcodes are moved from stage B to stage C, where they remain until the next instruc- tion is complete ...

Page 97

... Freescale Semiconductor, Inc. Total execution time is calculated using the expression: Where: ( Total clock periods per instruction T ( Clock periods used for internal operation I ( Clock periods used for program access P ( Clock periods used for operand access O Refer to the CPU16 Reference Manual (CPU16RM/AD) for more information on this topic ...

Page 98

... Freescale Semiconductor, Inc. Table 4-5 Exception Vector Table Vector Vector Number Address 0 0000 0002 0004 0006 4 0008 5 000A 6 000C 7 000E 8 0010 9 – E 0012 – 001C F 001E 10 0020 11 0022 12 0024 13 0026 14 0028 15 002A 16 002C 17 002E 18 0030 19 – 37 0032 – 006E 38 – FF 0070 – 01FE 4 ...

Page 99

... Freescale Semiconductor, Inc. 4.13.3 Exception Processing Sequence Exception processing is performed in four phases. Priority of all pending exceptions is evaluated and the highest priority exception is processed first. Processor state is stacked, then the CCR PK extension field is cleared. An exception vector number is acquired and converted to a vector address. The content of the vector address is load- ed into the PC and the processor jumps to the exception handler routine ...

Page 100

... Freescale Semiconductor, Inc. 4.13.5 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation. Asynchronous exceptions have higher priorities than synchronous excep- tions. Exception processing for multiple exceptions is completed by priority, from high- est to lowest. Priority governs the order in which exception processing occurs, not the order in which exception handlers are executed ...

Page 101

... Freescale Semiconductor, Inc. 4.14.1.1 IPIPE0/IPIPE1 Multiplexing Six types of information are required to track pipeline activity. To generate the six state signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1. The multiplexed signals have two phases. State signals are active low. ...

Page 102

... Freescale Semiconductor, Inc. Breakpoints on instructions that are flushed from the pipeline before execution are not acknowledged. Operand breakpoints are always acknowledged. There is no break- point acknowledge bus cycle when BDM is entered. Refer to knowledge Cycle for more information about breakpoints. 4.14.3 Opcode Tracking and Breakpoints Breakpoints are acknowledged after a tagged instruction has executed, that is, when the instruction is copied from pipeline stage B to stage C ...

Page 103

... Freescale Semiconductor, Inc. of BKPT or execution of the BGND instruction. IPIPE0 and IPIPE1 change function be- fore an exception signal can be generated. The development system must use FREEZE assertion as an indication that BDM has been entered. When BDM is exited, FREEZE is negated before initiation of normal bus cycles. IPIPE0 and IPIPE1 are valid when normal instruction prefetch begins ...

Page 104

... Freescale Semiconductor, Inc. 4.14.4.6 BDM Serial Interface The BDM serial interface uses a synchronous protocol similar to that of the Freescale serial peripheral interface (SPI). use BDM with a development system. INSTRUCTION REGISTER BUS RCV DATA LATCH SERIAL IN PARALLEL OUT PARALLEL IN SERIAL OUT STATUS EXECUTION ...

Page 105

... Freescale Semiconductor, Inc. 4.15 Recommended BDM Connection In order to use BDM development tools when an MCU is installed in a system, Freescale recommends that appropriate signal lines be routed to a male Berg connector or double-row header installed on the circuit board with the MCU. Refer to Figure 4-8 BDM Connector Pinout 4 ...

Page 106

... Freescale Semiconductor, Inc. 4-46 For More Information On This Product, CENTRAL PROCESSING UNIT Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 107

... Freescale Semiconductor, Inc. SYSTEM INTEGRATION MODULE This section is an overview of the system integration module (SIM). Refer to the SIM Reference Manual (SIMRM/AD) for a comprehensive discussion of SIM capabilities. Refer to D.2 System Integration Module map and register structure. 5.1 General The SIM consists of six functional blocks. ...

Page 108

... Freescale Semiconductor, Inc. Figure 5-1 System Integration Module Block Diagram 5.2 System Configuration The SIM configuration register (SIMCR) governs several aspects of system operation. The following paragraphs describe those configuration options controlled by SIMCR. 5.2.1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block ...

Page 109

... Freescale Semiconductor, Inc. 5.2.2 Interrupt Arbitration Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbi- tration between interrupt requests of the same priority is performed by serial conten- tion between IARB field bit values. Contention will take place whenever an interrupt request is acknowledged, even when there is only a single request pending. For an interrupt to be serviced, the appropriate IARB field must have a non-zero value ...

Page 110

... Freescale Semiconductor, Inc. 5.3 System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in clock rate during operation ...

Page 111

... Freescale Semiconductor, Inc. 5.3.1 Clock Sources The state of the clock mode (MODCLK) pin during reset determines the system clock source. When MODCLK is held high during reset, the clock synthesizer generates a clock signal from an external reference frequency. The clock synthesizer control reg- ister (SYNCR) determines operating frequency and mode of operation ...

Page 112

... Freescale Semiconductor, Inc fast or slow reference frequency is provided to the PLL from a source other than a crystal external system clock signal is applied through the EXTAL pin, the XTAL pin must be left floating. 5.3.2 Clock Synthesizer Operation V is used to power the clock circuits when the system clock is synthesized from DDSYN either a crystal or an externally supplied reference frequency ...

Page 113

... Freescale Semiconductor, Inc 0 NORMAL OPERATING ENVIRONMENT 1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION. 2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE. Figure 5-5 System Clock Filter Networks The synthesizer locks when the VCO frequency is equal the filter time constant and by the amount of difference between the two comparator inputs ...

Page 114

... Freescale Semiconductor, Inc. When a fast reference is used, three W bits are located in the PLL feedback path, en- abling frequency multiplication by a factor from one to eight. Three Y bits and the X bit are located in the VCO clock output path to provide the ability to slow the system clock without disturbing the PLL ...

Page 115

... Freescale Semiconductor, Inc. Table 5-2 16.78-MHz Clock Control Multipliers (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 000000 4 .03125 000001 8 .0625 000010 12 .09375 000011 16 .125 000100 20 .15625 000101 24 .1875 000110 28 .21875 000111 32 .25 001000 36 .21825 ...

Page 116

... Freescale Semiconductor, Inc. Table 5-2 16.78-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 100000 132 1.03125 100001 136 1.0625 100010 140 1.09375 100011 144 1.125 100100 148 1.15625 100101 152 1 ...

Page 117

... Freescale Semiconductor, Inc. Table 5-3 20.97-MHz Clock Control Multipliers (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 000000 4 .03125 000001 8 .0625 000010 12 .09375 000011 16 .125 000100 20 .15625 000101 24 .1875 000110 28 .21875 000111 32 .25 001000 36 .21825 ...

Page 118

... Freescale Semiconductor, Inc. Table 5-3 20.97-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 100000 132 1.03125 100001 136 1.0625 100010 140 1.09375 100011 144 1.125 100100 148 1.15625 100101 152 1 ...

Page 119

... Freescale Semiconductor, Inc. Table 5-4 25.17-MHz Clock Control Multipliers (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 000000 4 .03125 000001 8 .0625 000010 12 .09375 000011 16 .125 000100 20 .15625 000101 24 .1875 000110 28 .21875 000111 32 .25 001000 36 .21825 ...

Page 120

... Freescale Semiconductor, Inc. Table 5-4 25.17-MHz Clock Control Multipliers (Continued) (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus [W: Value) VCO Y Slow Fast 100000 132 1.03125 100001 136 1.0625 100010 140 1.09375 100011 144 1.125 100100 148 1.15625 100101 152 1 ...

Page 121

... Freescale Semiconductor, Inc. Table 5-5 16.78-MHz System Clock Frequencies (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO 000000 131 kHz 000001 262 000010 393 000011 524 000100 655 000101 786 000110 918 000111 1049 001000 1180 001001 ...

Page 122

... Freescale Semiconductor, Inc. Table 5-5 16.78-MHz System Clock Frequencies (Continued) (Shaded cells represent values that exceed 16.78 MHz specifications.) Modulus [W: Value) VCO 100000 4325 kHz 100001 4456 100010 4588 100011 4719 100100 4850 100101 4981 100110 5112 100111 5243 101000 5374 ...

Page 123

... Freescale Semiconductor, Inc. Table 5-6 System Clock Frequencies for a 20.97-MHz System (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus [W: VCO 000000 131 kHz 000001 262 000010 393 000011 524 000100 655 000101 786 000110 918 000111 1049 001000 1180 ...

Page 124

... Freescale Semiconductor, Inc. Table 5-6 System Clock Frequencies for a 20.97-MHz System (Continued) (Shaded cells represent values that exceed 20.97 MHz specifications.) Modulus [W: VCO 100000 4325 kHz 100001 4456 100010 4588 100011 4719 100100 4850 100101 4981 100110 5112 100111 5243 101000 ...

Page 125

... Freescale Semiconductor, Inc. Table 5-7 System Clock Frequencies for a 25.17-MHz System (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus [W: Value) VCO 000000 131 kHz 000001 262 000010 393 000011 524 000100 655 000101 786 000110 918 000111 1049 001000 ...

Page 126

... Freescale Semiconductor, Inc. Table 5-7 System Clock Frequencies for a 25.17-MHz System (Continued) (Shaded cells represent values that exceed 25.17 MHz specifications.) Modulus [W: Value) VCO 100000 4325 kHz 100001 4456 100010 4588 100011 4719 100100 4850 100101 4981 100110 5112 100111 5243 ...

Page 127

... Freescale Semiconductor, Inc. 5.3.3 External Bus Clock The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the E- clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devic- es and peripherals. ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen ...

Page 128

... Freescale Semiconductor, Inc. The internal oscillator which supplies the input frequency for the PLL always runs when a crystal is used. SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO USING EXTERNAL CLOCK? YES USE SYSTEM CLOCK AS SIMCLK IN LPSTOP? YES SET STSIM = 1 f simclk IN LPSTOP NO WANT CLKOUT ...

Page 129

... Freescale Semiconductor, Inc. SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO 1 LEAVE IMBCLK ON IN LPSTOP? YES SET STOP BITS FOR MODULES THAT WILL NOT BE ACTIVE IN LPSTOP 2 SET STCPU = imbclk sys IN LPSTOP NO USING EXTERNAL CLOCK? YES USE SYSTEM CLOCK AS SIMCLK IN LPSTOP? YES SET STSIM = 1 ...

Page 130

... Freescale Semiconductor, Inc. 5.4 System Protection The system protection block preserves reset status, monitors internal activity, and pro- vides periodic interrupt generation. CLOCK 9 2 PRESCALER Figure 5-8 System Protection 5.4.1 Reset Status The reset status register (RSR) latches internal MCU status during reset. Refer to 5 ...

Page 131

... Freescale Semiconductor, Inc. Table 5-8 Bus Monitor Period BMT[1: The monitor does not check DSACK response on the external bus unless the CPU16 initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter- nal to external bus cycles system contains external bus masters, an external bus monitor must be implemented and the internal-to-external bus monitor option must be disabled ...

Page 132

... Freescale Semiconductor, Inc. Both writes must occur before time-out in the order listed. Any number of instructions can be executed between the two writes. Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the software watchdog timing (SWT[1:0]) field in SYPCR. SWP determines system clock prescaling for the watchdog timer and determines that one of two options, either no prescaling or prescaling by a factor of 512, can be select- ed ...

Page 133

... Freescale Semiconductor, Inc. Table 5-10 Software Watchdog Divide Ratio SWP Figure 5 block diagram of the watchdog timer and the clock control for the pe- riodic interrupt timer. EXTAL XTAL FREEZE CRYSTAL 1 128 OSCILLATOR CLOCK SELECT AND DISABLE SOFTWARE WATCHDOG RESET LPSTOP SWE SWT1 ...

Page 134

... Freescale Semiconductor, Inc. The periodic interrupt timer modulus counter is clocked by one of two signals. When the PLL is enabled (MODCLK = 1 during reset), f cillator; f 128 is used with fast reference oscillator. When the PLL is disabled (MOD- ref CLK = 0 during reset), f ref in the periodic interrupt timer register (PITR) determines system clock prescaling for the periodic interrupt timer ...

Page 135

... Freescale Semiconductor, Inc. The PIRQL field is compared to the CPU16 interrupt priority mask to determine wheth- er the interrupt is recognized. of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt request of the same priority. The periodic timer continues to run when the interrupt is disabled. Table 5-12 Periodic Interrupt Priority PIRQL[2:0] The PIV field contains the periodic interrupt vector ...

Page 136

... Freescale Semiconductor, Inc DSACK1 DSACK0 R/W CS3 CS4 IRQ7 ADDR[17:0] DATA[15: CSBOOT CS0 1 CS1 CS2 NOTES: 1. ALL CHIP-SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16-BIT. Figure 5-10 MCU Basic System 5-30 For More Information On This Product ADDR[3:0] DATA[15:8] ADDR[17:1] DATA[15: ADDR[15:1] DATA[15:8] ...

Page 137

... Freescale Semiconductor, Inc. The external bus has 24 address lines and 16 data lines. ADDR[19:0] are normal ad- dress outputs; ADDR[23:20] follow the output state of ADDR19. The EBI provides dy- namic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long- word transfers. Port width is the maximum number of bits accepted or provided by the external memory system during a bus transfer ...

Page 138

... Freescale Semiconductor, Inc. 5.5.1.5 Read/Write Signal The read/write signal (R/W) determines the direction of the transfer during a bus cycle. This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa ...

Page 139

... Freescale Semiconductor, Inc. 5.5.1.9 Bus Error Signal The bus error signal (BERR) is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing requirements. Refer to 5.6.5 Bus Exception Control Cycles The internal bus monitor can generate the BERR signal for internal-to-internal and in- ternal-to-external transfers ...

Page 140

... Freescale Semiconductor, Inc. Table 5-15 Effect of DSACK Signals DSACK1 DSACK0 the CPU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob- tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles ...

Page 141

... Freescale Semiconductor, Inc. 5.5.3 Operand Alignment The EBI data multiplexer establishes the necessary connections for different combi- nations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during the current bus cycle ...

Page 142

... Freescale Semiconductor, Inc. Table 5-16 Operand Alignment Current Transfer Case Cycle 1 Byte to 8-bit port (even) 2 Byte to 8-bit port (odd) 3 Byte to 16-bit port (even) 4 Byte to 16-bit port (odd) Word to 8-bit port 5 (aligned) Word to 8-bit port 6 (misaligned) Word to 16-bit port 7 (aligned) Word to 16-bit port ...

Page 143

... Freescale Semiconductor, Inc. Descriptions are made in terms of individual system clock states, labelled {S0, S1, S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and does not correspond to any implemented machine state. A clock cycle consists of two successive states. Refer to more information on clock control timing. ...

Page 144

... Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO READ 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS AND DS (S1) DECODE DSACK (S3) LATCH DATA (S4) NEGATE AS AND DS (S5) START NEXT CYCLE (S0) Figure 5-12 Word Read Cycle Flowchart 5 ...

Page 145

... Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS (S1) PLACE DATA ON DATA[15:0] (S2) ASSERT DS AND WAIT FOR DSACK (S3) OPTIONAL STATE (S4) NO CHANGE TERMINATE OUTPUT TRANSFER (S5) 1) NEGATE DS AND AS ...

Page 146

... Freescale Semiconductor, Inc. Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle). At the appropriate time, chip- select logic asserts data size acknowledge signals ...

Page 147

... Freescale Semiconductor, Inc. FUNCTION CODE 2 0 BREAKPOINT ACKNOWLEDGE 2 0 LOW POWER STOP BROADCAST 2 0 INTERRUPT ACKNOWLEDGE Figure 5-14 CPU Space Address Encoding 5.6.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development. In M68HC16 Z-series MCUs, breakpoints are treated as a type of exception process- ing ...

Page 148

... Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW CPU16 ACKNOWLEDGE BREAKPOINT 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE ALL ONES ON ADDR[4:2] 5) SET ADDR1 TO ONE 6) SET SIZE TO WORD 7) ASSERT AS AND DS NEGATE NEGATE DSACK or BERR INITIATE HARDWARE BREAKPOINT PROCESSING Figure 5-15 Breakpoint Operation Flowchart 5 ...

Page 149

... Freescale Semiconductor, Inc Figure 5-16 LPSTOP Interrupt Mask Level 5.6.5 Bus Exception Control Cycles An external device or a chip-select circuit must assert at least one of the DSACK[1:0] signals or the AVEC signal to terminate a bus cycle normally. Bus exception control cycles are used when bus cycles are not terminated in the expected manner. There are two sources of bus exception control cycles. • ...

Page 150

... Freescale Semiconductor, Inc. Table 5-17 DSACK, BERR, and HALT Assertion Results Type of Control Termination Signal NORMAL DSACK BERR HALT HALT DSACK BERR HALT BUS ERROR DSACK 1 BERR HALT BUS ERROR DSACK 2 BERR HALT BUS ERROR DSACK 3 BERR HALT BUS ERROR DSACK ...

Page 151

... Freescale Semiconductor, Inc. The external bus interface does not latch data when an external bus cycle is terminated by a bus error. When this occurs during an in- struction prefetch, the IMB precharge state (bus pulled high, or $FF) is latched into the CPU16 instruction register, with indeterminate re- sults ...

Page 152

... Freescale Semiconductor, Inc. The halt operation has no effect on bus arbitration. However, when external bus arbi- tration occurs while the MCU is halted, address and control signals go into a high-im- pedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write signals revert to the previous driven states ...

Page 153

... Freescale Semiconductor, Inc. MCU GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) RE-ARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-17 Bus Arbitration Flowchart for Single Request 5.6.6.1 Show Cycles The MCU normally performs internal data transfers without affecting the external bus, but it is possible to show these transfers during debugging ...

Page 154

... Freescale Semiconductor, Inc. 5.7 Reset Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. The RESET input is synchronized to the system clock. If there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted ...

Page 155

... Freescale Semiconductor, Inc. Table 5-18 Reset Source Summary Type Source External External Power up EBI Software watchdog Monitor HALT Monitor Loss of clock Clock Test Test Internal single byte or aligned word writes are guaranteed valid for synchronous re- sets. External writes are also guaranteed to complete, provided the external configu- ration logic on the data bus is conditioned as shown in 5 ...

Page 156

... Freescale Semiconductor, Inc. 5.7.3.1 Data Bus Mode Selection All data lines have weak internal pull-up devices. When pins are held high by the in- ternal pull-ups, the MCU uses a default operating configuration. However, specific lines can be held low externally during reset to achieve an alternate configuration. ...

Page 157

... Freescale Semiconductor, Inc. The mode configuration drivers are conditioned with R/W and DS to prevent conflicts between external devices and the MCU when reset is asserted. If external RESET is asserted during an external write cycle, R/W conditioning (as shown in prevents corruption of the data during the write. Similarly, DS conditions the mode configuration drivers so that external reads are not corrupted when RESET is asserted during an external read cycle ...

Page 158

... Freescale Semiconductor, Inc. DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If DATA8 is held low during reset, these pins are assigned to I/O port E. DATA9 determines the function of interrupt request pins IRQ[7:1] and the clock mode select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned to I/O port F ...

Page 159

... Freescale Semiconductor, Inc. Table 5-20 Module Pin Functions 1 Module ADC CPU GPT QSM MCCI NOTES: 1. Module port pins may indeterminate state for milliseconds at power-up. 5.7.5 Pin State During Reset It is important to keep the distinction between pin function and pin electrical state clear. ...

Page 160

... Freescale Semiconductor, Inc. Pins that are not used should either be configured as outputs, or (if configured as inputs) pulled to the appropriate inactive state. This de- creases additional I ply level. 5.7.5.1 Reset States of SIM Pins Generally, while RESET is asserted, SIM pins either inactive high-impedance state or are driven to their inactive states. After RESET is released, mode selection occurs, and reset exception processing begins ...

Page 161

... Freescale Semiconductor, Inc. 5.7.6 Reset Timing The RESET input must be asserted for a specified minimum period for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset ...

Page 162

... Freescale Semiconductor, Inc. The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and MSTRST is asserted for at least four clock cycles, these modules reset. V ramp time and VCO frequency ramp time determine how long the four cy- DD cles take ...

Page 163

... Freescale Semiconductor, Inc. When TSC assertion takes effect, internal signals are forced to val- ues that can cause inadvertent mode selection. Once the output driv- ers change state, the MCU must be powered down and restarted before normal operation can resume. 5.7.9 Reset Processing Summary To prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle, and not at an instruction boundary ...

Page 164

... Freescale Semiconductor, Inc. 5.8 Interrupts Interrupt recognition and servicing involve complex interaction between the SIM, the CPU16, and a device or module requesting interrupt service. This discussion provides an overview of the entire interrupt process. Chip-select logic can also be used to re- spond to interrupt requests. Refer to 5 ...

Page 165

... Freescale Semiconductor, Inc. Interrupt requests are sampled on consecutive falling edges of the system clock. In- terrupt request input circuitry has hysteresis valid, a request signal must be as- serted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are pro- cessed at instruction boundaries or when exception processing of higher-priority inter- rupts is complete ...

Page 166

... Freescale Semiconductor, Inc. Although arbitration is intended to deal with simultaneous requests of the same inter- rupt level, it always takes place, even when a single source is requesting service. This is important for two reasons: the EBI does not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early by a bus error ...

Page 167

... Freescale Semiconductor, Inc. 3. Request priority is latched into the CCR IP field from the address bus. D. Modules or external peripherals that have requested interrupt service decode the priority value in ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration by IARB contention takes place. E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol- lowing ways: 1 ...

Page 168

... Freescale Semiconductor, Inc DSACK1 DSACK0 R/W CS3 CS4 IRQ7 ADDR[17:0] DATA[15: CSBOOT CS0 1 CS1 CS2 NOTES: 1. ALL CHIP-SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16-BIT. Figure 5-21 Basic MCU System 5-62 For More Information On This Product ADDR[3:0] DATA[15:8] ADDR[17:1] DATA[15: ADDR[15:1] DATA[15:8] ...

Page 169

... Freescale Semiconductor, Inc. Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Logic can also generate DSACK and AVEC signals internally. A single DSACK generator is shared by all chip- selects. Each signal can also be synchronized with the ECLK signal available on ADDR23 ...

Page 170

... Freescale Semiconductor, Inc. Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register (CSBAR[10:0] and CSBARBT). However, because the logic state of ADDR20 is al- ways the same as the state of ADDR19 in the MCU, the largest usable block size is 512 Kbytes ...

Page 171

... Freescale Semiconductor, Inc. Port size determines the way in which bus transfers to an external address are allo- cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. Port size and transfer size affect how the chip-select signal is asserted. ...

Page 172

... Freescale Semiconductor, Inc. The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be an integer multiple of the block size. Because the logic state of ADDR[23:20] follows that of ADDR19 in the CPU16, maxi- mum block size is 512 Kbytes, and addresses from $080000 to $F7FFFF are inacces- sible ...

Page 173

... Freescale Semiconductor, Inc. SPACE[1:0] determines the address space in which a chip-select is asserted. An ac- cess must have the space type represented by the SPACE[1:0] encoding in order for a chip-select signal to be asserted. IPL[2:0] contains an interrupt priority mask that is used when chip-select logic is set to trigger on external interrupt acknowledge cycles. When SPACE[1:0] is set to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to the IPL field ...

Page 174

... Freescale Semiconductor, Inc. 5.9.3 Using Chip-Select Signals for Interrupt Acknowledge Ordinary bus cycles use supervisor or user space access, but interrupt acknowledge bus cycles use CPU space access. Refer to rupts for more information. There are no differences in flow for chip selects in each type of space, but base and option registers must be properly programmed for each type of external bus cycle ...

Page 175

... Freescale Semiconductor, Inc. 4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte when using an 8-bit port interrupting device does not provide a vector number, an autovector acknowledge must be generated, either by asserting the AVEC pin or by generating AVEC internally using the chip-select option register ...

Page 176

... Freescale Semiconductor, Inc. However, the internal pull-up driver can be overcome by bus loading effects. To en- sure a particular configuration out of reset, use an active device to put DATA0 in a known state during reset. The base address field in the boot chip-select base address register CSBARBT has a reset value of all zeros, so that when the initial access to address $000000 is made, an address match occurs, and the CSBOOT signal is asserted ...

Page 177

... Freescale Semiconductor, Inc. 5.10.3 Data Registers A write to the port E and port F data registers (PORTE[0:1] and PORTF[0:1]) is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of a data register returns the value at the pin only if the pin is configured as a discrete input ...

Page 178

... Freescale Semiconductor, Inc. 5-72 For More Information On This Product, SYSTEM INTEGRATION MODULE Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 179

... Freescale Semiconductor, Inc. STANDBY RAM MODULE The standby RAM (SRAM) module consists of a fixed-location control register block and an array of fast (two clock) static RAM that may be mapped to a user specified location in the system memory map. Array size depends on the M68HC16, M68CK16, and M68CM16 Z-series version ...

Page 180

... Freescale Semiconductor, Inc. 6.2 SRAM Array Address Mapping Base address registers RAMBAH and RAMBAL are used to specify the SRAM array base address in the memory map. RAMBAH and RAMBAL can only be written while the SRAM is in low-power stop mode (RAMMCR STOP = 1) and the base address lock (RAMMCR RLCK = 0) is disabled. RLCK can be written once only to a value of one ...

Page 181

... Freescale Semiconductor, Inc. I (SRAM standby current) values may vary while V SB PENDIX A ELECTRICAL CHARACTERISTICS sumption specifications. 6.6 Reset Reset places the SRAM in low-power stop mode, enables program space access, and clears the base address registers and the register lock bit. These actions make it pos- sible to write a new base address into the ROMBAH and ROMBAL registers ...

Page 182

... Freescale Semiconductor, Inc. 6-4 For More Information On This Product, STANDBY RAM MODULE Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 183

... Freescale Semiconductor, Inc. MASKED ROM MODULE The masked ROM module (MRM) is only available with the MC68HC16Z2 and the MC68HC16Z3. The MRM consists of a fixed-location control register block and an 8- Kbyte mask-programmed read-only memory array that can be mapped to any 8-Kbyte boundary in the system memory map. The MRM can be programmed to insert wait states to match slower external development memory ...

Page 184

... Freescale Semiconductor, Inc. The MRM array can be mapped to any 8-Kbyte boundary in the memory map, but must not overlap other module control registers (overlap makes the registers inaccessible). If the array overlaps the MRM register block, addresses in the register block are ac- cessed instead of the corresponding ROM array addresses. ...

Page 185

... Freescale Semiconductor, Inc. WAIT[1: Refer to 5.6 Bus Operation 7.5 Low-Power Stop Mode Operation Low-power stop mode minimizes MCU power consumption. Setting the STOP bit in MRMCR places the MRM in low-power stop mode. In low-power stop mode, the array cannot be accessed. The reset state of STOP is the complement of the logic state of DATA14 during reset ...

Page 186

... Freescale Semiconductor, Inc. 7-4 For More Information On This Product, MASKED ROM MODULE Go to: www.freescale.com M68HC16 Z SERIES USER’S MANUAL ...

Page 187

... Freescale Semiconductor, Inc. ANALOG-TO-DIGITAL CONVERTER This section is an overview of the analog-to-digital converter module (ADC). Refer to the ADC Reference Manual (ADCRM/AD) for a comprehensive discussion of ADC ca- pabilities. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS and electrical specifications. Refer to register address mapping and bit/field definitions. 8.1 General The ADC is a unipolar, successive-approximation converter with eight modes of oper- ation ...

Page 188

... Freescale Semiconductor, Inc. MODE AND TIMING CONTROL Figure 8-1 ADC Block Diagram 8.2.1 Analog Input Pins Each of the eight analog input pins (AN[7:0]) is connected to a multiplexer in the ADC. The multiplexer selects an analog input for conversion to digital data. Analog input pins can also be read as digital inputs, provided the applied voltage ...

Page 189

... Freescale Semiconductor, Inc. 8.2.2 Analog Reference Pins Separate high (V ) and low (V RH alog reference pins. The pins permit connection of regulated and filtered supplies that allow the ADC to achieve its highest degree of accuracy. 8.2.3 Analog Supply Pins Pins V and V supply power to analog circuitry associated with the RC DAC. ...

Page 190

... Freescale Semiconductor, Inc. STOP is set during system reset, and must be cleared before the ADC can be used. Because analog circuit bias currents are turned off during low-power stop mode, the ADC requires recovery time after STOP is cleared. Execution of the CPU16 LPSTOP command places the entire modular microcontroller in low-power stop mode ...

Page 191

... Freescale Semiconductor, Inc. Table 8-2 Multiplexer Channel Sources [CD:CA] Value 8.6.2 Sample Capacitor and Buffer Amplifier Each of the eight external input channels is associated with a sample capacitor and share a single sample buffer amplifier. After a conversion is initiated, the multiplexer output is connected to the sample capacitor at the input of the sample buffer amplifier for the first two ADC clock cycles of the sampling period ...

Page 192

... Freescale Semiconductor, Inc. 8.6.4 Comparator The comparator indicates whether each approximation output from the RC DAC array during resolution is higher or lower than the sampled input voltage. Comparator output is fed to the digital control logic, which sets or clears each bit in the successive approx- imation register in sequence, MSB first. ...

Page 193

... Freescale Semiconductor, Inc. PRS[4:0] %00000 %00001 System Clock/4 %00010 System Clock/6 %00011 System Clock/8 %11101 System Clock/60 %11110 System Clock/62 %11111 System Clock/64 ADC clock speed must be between 0.5 MHz and 2.1 MHz. The reset value of the PRS field is %00011, which divides a nominal 16.78 MHz system clock by eight, yielding maximum ADC clock frequency ...

Page 194

... Freescale Semiconductor, Inc. 8.7.5.1 Conversion Parameters Table 8-5 describes the conversion parameters controlled by bits in ADCTL1. Table 8-5 Conversion Parameters Controlled by ADCTL1 Conversion Parameter Conversion channel Length of sequence Single or continuous conversion Single or multiple channel conversion 8.7.5.2 Conversion Modes Conversion modes are defined by the state of the SCAN, MULT, and S8CM bits in ADCTL1 ...

Page 195

... Freescale Semiconductor, Inc. Mode 2 — A single conversion is performed on each of four sequential input channels, starting with the channel specified by the value in CD:CA. Each result is stored in a separate result register (RSLT0 to RSLT3). The appropriate CCF bit in ADCSTAT is set as each register is filled. The SCF bit in ADCSTAT is set when the last conversion is complete. Mode 3 — ...

Page 196

... Freescale Semiconductor, Inc. Table 8-7 Single-Channel Conversions (MULT = 0) S8CM NOTES: 1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read. ANALOG-TO-DIGITAL CONVERTER 8-10 For More Information On This Product, CA Input 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 0 Reserved 1 Reserved 0 Reserved ...

Page 197

... Freescale Semiconductor, Inc. Table 8-8 Multiple-Channel Conversions (MULT = 1) S8CM NOTES: 1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read. M68HC16 Z SERIES ANALOG-TO-DIGITAL CONVERTER USER’S MANUAL For More Information On This Product, CA Input X AN0 AN1 AN2 AN3 X AN4 AN5 AN6 ...

Page 198

... Freescale Semiconductor, Inc. 8.7.6 Conversion Timing Total conversion time is made up of initial sample time, transfer time, final sample time, and resolution time. Initial sample time is the time during which a selected input chan- nel is connected to the sample buffer amplifier through a sample capacitor. During transfer time, the sample capacitor is disconnected from the multiplexer, and the RC DAC array is driven by the sample buffer amp ...

Page 199

... Freescale Semiconductor, Inc. INITIAL FINAL SAMPLE TRANSFER SAMPLE TIME TIME TIME (2 ADC CLOCKS CYCLES SAMPLE AND TRANSFER PERIOD SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4-CHANNEL MODE Figure 8-3 10-Bit Conversion Timing 8.7.7 Successive Approximation Register The successive approximation register (SAR) accumulates the result of each conver- sion one bit at a time, starting with the most significant bit ...

Page 200

... Freescale Semiconductor, Inc. Table 8-9 Result Register Formats Result Data Format Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution, Unsigned bits [7:0] are used for 8-bit conversion (bits [9:8] are zero). Bits [15:10] always return zero right-justified format when read ...

Related keywords