MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 246

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.3.1 SPI Registers
10.3.1.1 SPI Control Register (SPCR)
10.3.1.2 SPI Status Register (SPSR)
10.3.1.3 SPI Data Register (SPDR)
10.3.2 SPI Pins
10-6
Error-detection logic is included to support interprocessor interfacing. A write-collision
detector indicates when an attempt is made to write data to the serial shift register
while a transfer is in progress. A multiple-master mode-fault detector automatically dis-
ables SPI output drivers if more than one MCU simultaneously attempts to become
bus master.
SPI control registers include the SPI control register (SPCR), the SPI status register
(SPSR), and the SPI data register (SPDR). Refer to
D.7.14 SPI Status
definitions.
The SPCR contains parameters for configuring the SPI. The register can be read or
written at any time.
The SPSR contains SPI status information. Only the SPI can set the bits in this regis-
ter. The CPU reads the register to obtain status information.
The SPDR is used to transmit and receive data on the serial bus. A write to this register
in the master device initiates transmission or reception of another byte or word. After
a byte or word of data is transmitted, the SPIF status bit is set in both the master and
slave devices.
A read of the SPDR actually reads a buffer. If the first SPIF is not cleared by the time
a second transfer of data from the shift register to the read buffer is initiated, an over-
run condition occurs. In cases of overrun the byte or word causing the overrun is lost.
A write to the SPDR is not buffered and places data directly into the shift register for
transmission.
Four bidirectional pins are associated with the SPI. The MPAR configures each pin for
either SPI function or general-purpose I/O. The MDDR assigns each pin as either input
or output. The WOMP bit in the SPI control register (SPCR) determines whether each
SPI pin that is configured for output functions as an open-drain output or a normal
CMOS output. The MDDR and WOMP assignments are valid regardless of whether
the pins are configured for SPI use or general-purpose I/O.
The operation of pins configured for SCI use depends on whether the SCI is operating
as a master or a slave, determined by the MSTR bit in the SPCR.
Table 10-3
shows SPI pins and their functions.
MULTICHANNEL COMMUNICATION INTERFACE
Register, and
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D.7.15 SPI Data Register
D.7.13 SPI Control
for register bit and field
M68HC16 Z SERIES
USER’S MANUAL
Register,