MC68HC16Z1CFC16 Freescale Semiconductor, MC68HC16Z1CFC16 Datasheet - Page 489

• Manufacturer Part Number: MC68HC16Z1CFC16
• Description: IC MPU 1K RAM 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CFC16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Instruction
Intermodule bus (IMB) 3-2,
Internal
Interrupt
Interrupts
Inter-transfer delay
INTV D-40,
I
IP 4-4, 9-3,
IPA
IPIPE0
IPIPE1
IPIPE1/0 5-53
IPL
IRQ 5-58,
I
IX
IY
IZ
Junction leakage
M68HC16 Z SERIES
USER’S MANUAL
OUT
SB
4-3
4-3
4-3
6-3
D-21
D-68
execution model
fetches
pipeline
set for CPU16
timing
bus
register map
VCO frequency
acknowledge
arbitration 5-3, 9-3,
exception processing
level (IL)
priority
processing summary
vector
GPT
MCCI
QSM
SIM 5-58
8-19
4-43
4-43
error (BERR) 5-24,
monitor
and arbitration
bus cycles 5-61
IARB field
for QSPI (ILQSPI)
for SCI (ILSCI)
adjust (IPA)
and recognition 5-58
level field (IPL) 5-67,
mask (IP) field 4-4, 5-58, 9-3, 11-6,
number 9-3,
11-5
9-3
5-60
10-3
4-36
D-56
D-3
D-56
4-7
4-35
GPT
MCCI
QSM
SIM 5-59,
field (INTV)
5-24
8-23
3-16
D-68
4-11
D-39
9-6
D-55
5-8
D-68
4-35
11-6
D-7
5-59
11-6
D-40
D-40
–J–
5-60
5-58
11-1
D-40
5-25
D-21
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D-3
Leakage error
Length of delay after transfer (DTL)
Level-sensitivity 5-58
LJSRR
LJURR
LOC
LOCK 7-3,
Lock registers (LOCK)
Logic
Loop mode (LOOPS) D-41,
LOOPQ
LOOPS D-41, D-61
Loss of clock reset (LOC)
Low-power
LPSTOP 5-21, 5-29
LSB
LSBF
LSW
M 9-25, 10-18, D-42, D-61
M68HC11 instructions compared to CPU16 instructions
M68HC16Z1EVB evaluation board
M68MEVB1632 modular evaluation board (MEVB)
M68MMDS1632 modular development system (MMDS)
MAC 4-5, 4-9,
Masked ROM module (MRM). See MRM
Master/slave mode select (MSTR)
Maximum ratings (electricals)
MCCI
analyzer pod connectors
levels (definition)
broadcast cycle
CPU space cycle
interrupt mask level
operation — SIM 5-29
stop mode enable (STOP)
address map
address map information
block diagram
features
general
general-purpose I/O
initialization
interrupts
pin function
reference manual
registers
2-6
D-8
2-6
10-11
D-36
D-37
D-50
ADC 8-3,
GPT 11-3,
MCCI 10-2,
MRM 7-3,
QSM 9-2,
SRAM 6-2,
4-31
C-1
D-26
10-1
3-2
8-23
4-45
10-3
D-58
10-23
D-54
D-30
D-39
10-1
D-25
D-68
D-23
5-42
D-55
2-6
5-42
10-1
D-26
5-42
10-4
–M–
–L–
D-8
D-61
C-2
A-1
10-2
D-46
E-1
D-49
7-1
C-2
I-7