M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 158

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Table 18.2 Specifications of UART Mode (2)
1 .
Error detection
Select function
0
C
Note: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
9
0 .
8 /
B
0
0
0
1
A
G
8
u
the UARTi receive interrupt request bit will not change.
7
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0 -
u
1
0
Item
p
0
, 2
0
2
0
0
5
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• Overrun error (Note)
• Framing error
• Parity error
• Error sum flag
• Separate CTS/RTS pins (UART0)
• Sleep mode selection (UART0, UART1)
• Serial data logic switch (UART2 to UART4)
• TxD, RxD I/O polarity switch (UART2 to UART4)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
UART0 CTS and RTS pins each can be assigned to separate pins
This mode is used to transfer data to and from one of multiple slave micro-
computers
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
f o
3
2
9
_______
_______ _______
_______
18. Clock asynchronous serial I/O (UART) mode
Specification