M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 164

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
Table 19.1 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Note 1: ‘n’ denotes the value 00
Note 2: f
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi
1 .
Transfer data format
Transfer clock
Transmission / reception control
Other settings
Transmission start condition
Reception start condition
Error detection
0
C
19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
Interrupt request
generation timing
9
0 .
8 /
B
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some
extra settings in UART2 to UART4 clock-asynchronous serial I/O mode allows the user to effect this function.
Table 19.1 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
0
0
0
1
A
G
8
receive interrupt request bit will not change.
u
EXT
7
o r
. g
0 -
u
1
0
is input from the CLKi pin.
Item
p
0
, 2
0
2
0
0
5
Page 151
19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)
• Transfer data 8-bit UART mode (bit 2 to 0 of addresses 0338
• One stop bit (bit 4 of addresses 0338
• With the direct format chosen
• With the inverse format chosen
• With the internal clock chosen (bit 3 of addresses 0338
• With an external clock chosen (bit 3 of addresses 0338
• Disable the CTS and RTS function (bit 4 of address 033C
• The sleep mode select function is not available for UART2 and UART3
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 033D
• Set N-channel open drain output to TxD and RxD pins in UART3 and 4 (bit 5 of
• To start transmission, the following requirements must be met:
• To start reception, the following requirements must be met:
• When transmitting
• When receiving
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
16
Set parity to “even” (bit 5 and 6 of addresses 0338
Set data logic to “direct” (bit 6 of address 033D
Set transfer format to LSB (bit 7 of address 033C
Set parity to “odd” (bit 5 and 6 of addresses 0338
Set data logic to “inverse” (bit 6 of address 033D
Set transfer format to MSB (bit 7 of address 033C
032D
address 032C
- Transmit enable bit (bit 0 of address 033D
- Transmit buffer empty flag (bit 1 of address 033D
- Reception enable bit (bit 2 of address 033D
- Detection of a start bit
When data transmission from the UART2 to UART4 transfer register is completed (bit
4 of address 033D
When data transfer from the UART2 to UART4 receive register to the UART2 to
UART4 receive buffer register is completed
- On the reception side, an “L” level is output from the TxD
- On the transmission side, a parity error is detected by the level of input to the RxD
: fi / 16 (n + 1)
: f
f o
error signal output function (bit 7 of address 033D
parity error is detected
pin when a transmission interrupt occurs
to FF
EXT
3
2
16
9
/ 16 (n+1)
16
, 02FD
that is set to the UARTi bit rate generator.
_______
16
16
, 02FC
= “1”)
16
, 032D
_______
16
(Note 1) : fi=f
(Note 1) (Note 2)
= “1”)
16
, 02FD
Specification
16
16
1
, f
= “1”)
, 0328
8
, f
32
16
16
16
16
16
, 0328
, 032D
, 0328
, 02F8
16,
, 032D
16,
16,
16,
032D
16
16
16
16
032D
032C
16
, 032D
16
16
032C
, 032D
, 02F8
, 02F8
16
, 02FD
, 0328
16
16
= “0”)
16,
, 02FD
, 0328
, 0328
16,
16
16,
16,
i
02FD
16
16
16
pin by use of the parity
, 032C
16
16
02FD
02FC
= “0” and “1” respectively)
16
= “1” and “1” respectively)
02FC
, 02FD
, 02FD
, 02F8
16
16
16
) = “1”
16
, 02F8
, 02F8
) = “1”
16
16
16
= “0”).
16
16
16
, 02FC
= “1”)
16
= “0”).
= “101
= “1”)
) = “0”
16
16
= “1”) when a
= “0”)
= “1”)
2
16
”)
= “1”)
16
,
i