M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 295

IC M16C MCU FLASH 128K 144LQFP

M30802FCGP#D3

Manufacturer Part Number
M30802FCGP#D3
Description
IC M16C MCU FLASH 128K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet

Specifications of M30802FCGP#D3

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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M
R
R
e
E
1
v
J
6
Figure 30.5 Block erase flowchart
1 .
0
C
9
0 .
8 /
B
0
0
Block Erase Command (20
0
1
A
By writing the command code “20
in the second bus cycle that follows to the block address of a flash memory block, the system initiates
an auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned
to 1 upon completion of the auto erase operation. In this case, the read status register mode remains
active until the Read Array command (FF
flash memory is reset using its reset bit.
The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1
when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 30.5 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.
8
G
u
7
o r
. g
0 -
u
1
0
p
0
, 2
0
2
____
0
0
5
Page 282
f o
3
16
2
9
/D0
Check full status check
16
16
RY/BY status flag
)
” in the first bus cycle and the confirmation command code “D0
Block address
Write D0
Block erase
Write 20
completed
16
Start
= 1?
) or Read Lock Bit Status command (71
YES
16
16
NO
30. CPU Rewrite Mode
16
) is written or the
16

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