M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 348

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
1
6
Version
C
8 /
0
G
o r
Page 25 Figure 1.6.1, 1.6.2 Figure 1.6.1 is divided to Figure 1.6.1and 1.6.2
Page 30 Table 1.7.4
Page 34 Figure 1.7.3
Page 36 Line 3
Page 38, 39 Figure 1.7.6, 1.7.7
Page 42 Line 7 addition
Page 42 (3)BCLK When shifting to stop mode, --> When main clock is stoped or shifting to
Page 43 Figure 1.8.4
Page 44 Figure 1.8.5
Page 48 Line 5
Page 51 Figure 1.8.7. Clock transition
Page 52 Line 9 addition
Page 54 Software Interrupts (2) Overflow interrupt, "CMPX" addition
Page 55 (2) Peripheral I/O interrupts
Page 57 • Variable vector tables addition
Page 58 Table 1.9.3
Page 58 Table 1.9.3, page 68 Figure 1.9.8
Page 71 Address match interrupt Line 7 addition
Page 72 (3) The NMI interrupt
Page 72 (4) External interrupt
Page 74 Figure 1.10.1
Page 76 Line 2
Page 76 Line 12 addition
Page 76 Figure 1.11.1
Page 77 Table 1.11.1
u
p
_______
When the main clock is stoped (bit 5 at address 0006
stop mode (bit 0 at address 0007
000C
stop mode,
reset or stopping main clock,
(12) Low power dissipation mode addition
When the main clock is stoped, the main clock division register (address 000C
set to the division by 8 mode.
• Bus collision detection/start, stop condition (UART2, UART3, UART4) interrupts -->
change
Set an even address to the start address of vector table setting in INTB so that
operating efficiency is increased.
Bus collision detection/start, stop condition interrupts --> Bus collision detection, start/
stop condition detection interrupts
Software interrupt number 40, 41 fault errir --> addition
• Do not reset the CPU with the input to the NMI pin being in the “L” state. --> • Signal
of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for
NMI pin.
"DMAC is a function that to transmit 1 data of a source address (8 bits /16 bits) to a
destination address when transmission request occurs. " addition.
When writing to DSA2 and DSA3, set register bank select flag (B flag) to "1" and use
LDC instruction to set SB and FB registers.
16
) is set to the divided-8 mode.
_______
the chip select control register --> the wait control registe
When shifting to stop mode and reset, --> When shifting to stop mode,
Note addition
CM0 Note 6 change, Note 7, 8 addition, CM1 Note 4 addition
Note 2 change
Transfer memory space (16 Mbyte space) --> addition
Note change
Contents for change
16
Note 3, 4 addition
=1), the main clock division register (address
C - 6
_______
16
=1) or the mode is shifted to
16
) is
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