M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 175

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
Figure 20.5 Serial bus communication control example using the SSi input pins
1 .
0
C
(2) Serial Interface Special Function
9
0 .
8 /
B
UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure 20.5).
The master outputting the transfer clock transfers data to the slave inputting the transfer clock. In this
case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/
masters using the SSi input pins. Figure 20.6 shows the structure of UARTi special mode register 3
(addresses 0325
SSi input pins function between the master and slave are as follows.
_____
0
0
0
< Slave Mode (STxDi and SRxDi are selected, DINC = 1) >
< Master Mode (TxDi and RxDi are selected, DINC = 0) >
1
A
8
G
When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high
impedance, hence clock input is ignored. When an "L" level signal is input to an SSi input pin, clock
input becomes effective and serial communications are enabled. (i = 3 or 4)
The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis-
sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin,
another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the
trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble error
is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi trans-
mission-reception mode register (address 0328
The trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection
interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of UARTi special mode
register 3 (address 0325
When the trouble error flag is set to “0”, output is restored to the clock output and data output pins. In
the master mode, if an SSi input pin is H level, “0” can be written for the trouble error flag. When an SSi
input pin is L level, “0” cannot be written for the trouble error flag. In the slave mode, the “0” can be
written for the trouble error flag regardless of the input to the SSi input pins.
u
7
o r
. g
0 -
u
1
0
_____
p
0
, 2
0
2
0
0
5
Page 162
16
_____
and 02F5
M16C/80 (M)
M :Master
S :Slave
_____
IC1
P9
P9
P9
f o
P9
16
1(
0(
2(
16
3
3(
RxD
CLK
TxD
and 02F5
2
SS
P1
P1
[i = 3 or 4]) which controls this mode.
9
3
3
3
3
3
2
)
)
)
)
16
_____
[i = 3 or 4]) to “1”.
16
20. UARTi Special Mode Register (i = 2 to 4)
and 02F8
P9
P9
P9
P9
P9
P9
P9
P9
0(
2(
0(
2(
3(
3(
1(
1(
16
M16C/80 (S)
M16C/80 (S)
SS
CLK
SRxD
SS
CLK
SRxD
STxD
STxD
_____
[i = 3 or 4]) to “0”.
3
3
IC2
IC3
)
)
3
3
)
)
3
3
3
3
)
)
)
)
_____
_____
_____
_____