M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 40

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
Figure 6.1 Processor mode register 0
1 .
0
C
9
0 .
8 /
Processor mode register 0 (Note 1)
B
b7
0
0
0
1
A
G
8
b6
0
u
7
o r
. g
0 -
b5
u
1
0
p
0
Note 1: Set bit 1 of the protect register (address 000A
Note 2: If the V
Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when
Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a
Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in
Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 7: When using 16-bit bus width in DRAM controller, set this bit to "1".
Note 8: Do not set the processor mode bits and other bits simultaneously when setting the processor mode
, 2
b4
0
2
b3 b2
0
0
5
to “1” and PM07 is set to “0”.)
mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and
bit 1 (CM01) of system clock control register 0 (address 0006
bits to “01
Page 27
b1
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
b0
CC
2
voltage is applied to the CNV
” or “11
Reserved bit
Bit symbol
PM01
PM02
PM03
PM04
PM05
PM07
PM00
f o
Symbol
PM0
3
2
2
”. Set the other bits first, and then change the processor mode bits.
9
Software reset bit
Processor mode bit
Multiplexed bus space
select bit (Note 3)
BCLK output disable bit
(Note 5)
(Note 8)
R/W mode select bit
(Note 7)
Address
0004
Bit name
SS
16
, the value of this register when reset is 03
16
) to “1” when writing new values to this register.
80
When reset
16
The device is reset when this bit is set to “1”.
The value of this bit is “0” when read.
b5 b4
Must always be set to “0”
0 : BCLK is output (Note 6)
1 : Function set by bit 0,1 of system
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
(Note 2)
clock control register 0
16
) = "0". "L" is now output from P5
Function
6. Processor Mode
16
. (PM00 is set
R
3
.
W