M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 196

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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25. DRAM Controller
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Table 25.1 DRAM Controller Functions
1 .
Figure 25.1 DRAM control register
0
C
There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of
DRAM. Table 25.1 shows the functions of the DRAM controller.
DRAM space
Bus control
Refresh
Function modes
Waits
To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 0040
to specify the DRAM size. Figure 25.1 shows the DRAM control register.
The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 0005
Always use the DRAM controller in external memory modes 0, 1, or 2.
When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 0004
Set wait time between after DRAM power ON and before memory processing, and processing necessary
for dummy cycle to refresh DRAM by software.
9
0 .
8 /
B
DRAM control register
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
1
A
G
8
u
7
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0 -
u
1
0
p
0
, 2
0
2
0
0
5
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________
512KB, 1MB, 2MB, 4MB, 8MB
2CAS/1W
CAS before RAS refresh
Self refresh-compatible
EDO-compatible, fast page mode-compatible
1 wait or 2 waits, programmable
Note 1: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1.
Note 2: When you set "1", both RAS and CAS change to "L". When you set "0",
Note 3: Set the bus width using the external data bus width control register (address
Note 4: After reset, the content of this register is indeterminate.
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
Bit symbol
WT
AR0
AR2
AR1
SREF
f o
3
DRAMCONT
2
9
RAS and CAS change to "H" and then normal operation (read/write, refresh)
is resumed. In Stop mode, there is no control.
000B
DRAM controller starts the operation after writing to this register.
Symbol
________
16
Self-refresh mode bit
(Note 2)
Wait select bit (Note 1)
). When selecting 8-bit bus width, CASH is indeterminate.
DRAM space select bit
Bit name
Address
00040
16
Indeterminate (Note 4)
b3 b2 b1
0: Self-refresh OFF
1: Self-refresh ON
0 : Two wait
1 : One wait
0 0 0 : DRAM ignored
0 0 1 : Inhibit
0 1 0 : 0.5MB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Inhibit
When reset
Function
25. DRAM Controller
16
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R
W
16
2
16
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