M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 67

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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R
R
e
E
1
v
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Figure 8.7 Clock transition
6
1 .
0
C
9
0 .
8 /
B
Transition of stop mode, wait mode
Transition of normal mode
0
0
0
High-speed/medium-speed mode
Low-speed/low power dissipation mode
1
All oscillators stopped
All oscillators stopped
A
8
G
Note 1: Switch clocks after oscillation of main clock is fully stable.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: When shifting to division by 8 mode, MCD is set to "08
u
7
Low power
dissipation mode
Main clock is stopped
Sub clock is oscillating
o r
Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped,
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: The main ckock devision register is set to the division by 8 mode (MCD="08
Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="08
Main clock is oscillating
Sub clock is stopped
. g
0 -
Medium-speed mode
(divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode)
Stop mode
Stop mode
High-speed mode
BCLK :f(X
u
1
Please change according to a direction of an arrow.
CM07=“0” MCD=“XX
0
CM07=“0” MCD=“12
p
0
, 2
0
transferred to the middle speed mode.
2
BCLK :f(X
0
Note 4
0
IN
5
)
/division rate
Page 54
IN
BCLK :f(X
)
CM07=“1”
16
Interrupt
16
CM10=“1”
CM10=“1”
Interrupt
CM10=“1”
Note 3
Interrupt
”
”
CM07=“0”
MCD=“XX
CM04=“1”
MCD=“XX
Note 1, 3
CIN
f o
)
3
2
9
16
16
”
”
Note 1
Note 3
High-speed/medium-
Low-speed/low power
Medium-speed mode
(Divided-by-8 mode)
dissipation mode
Normal mode
CM05=“0”
Note 1
speed mode
(Please see the following as transition of normal mode.)
CM05=“1”
Reset
CM04=“0”
CM04=“1”
16
Note 4
".
Note 4
Note 1
Note 2
Main clock is oscillating
Sub clock is oscillating
Medium-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
High-speed mode
BCLK :f(X
CM07=“0” MCD=“XX
CM07=“0” MCD=“12
Medium-speed mode (divided-by-8 mode)
Main clock is oscillating
Sub clock is stopped
WAIT
instruction
WAIT
instruction
Interrupt
BCLK :f(X
Interrupt
WAIT
instruction
Interrupt
Note 4
IN
CM07=“0
MCD=“XX
Main clock is oscillating
Sub clock is oscillating
16
)
Low-speed mode
/division rate
").
CM07=“0” MCD=“08
IN
BCLK :f(X
BCLK :f(X
)
CM07=“1”
16
8. Clock Generating Circuit
Note 1
16
”
16
”
Note 3
”
CPU operation stopped
CPU operation stopped
CPU operation stopped
CIN
CM04=“1”
MCD=“XX
Note 1, 3
IN
Wait mode
Wait mode
Wait mode
)/8
)
16
”
16
”
CM07=“1”
Note 2
16
").