M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 58

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
(2) Sub clock
(3) BCLK
(4) Peripheral function clock
(5) f
(6) f
Figure 8.4 shows the system clock control registers 0 and 1 and Figure 8.5 shows main clock division
register.
C
9
0 .
8 /
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
the sub clock oscillation as CPU operating clock source before stopping the clock reduces the power
dissipation.
When the main clock is stoped (bit 5 at address 0006
address 0007
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the X
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
defaults to “1” when shifting from high-speed or middle-speed mode to stop mode and after a reset.
This bit remains in low-speed and low power dissipation mode.
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 0006
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock
oscillation circuit can be reduced using the X
Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
When the sub clock is used, set ports P8
The BCLK is the clock that drives the CPU, and is either fc or is derived by dividing the main clock by 1,
2, 3, 4, 6, 8, 10, 12, 14 or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
This signal is output from BCLK pin using CM01, CM00 and PM07 in memory expansion mode and
microprocessor mode.
When main clock is stoped or shifting to stop mode, the main clock division register (address 000C
set to the division by 8 ("08
• f
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 0006
• f
This clock has the same frequency as the main clock and is used for A/D conversion.
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
This clock has the same frequency as the sub clock. It is used for BCLK and for the watchdog timer.
B
0
0
0
1
AD
1
, f
C32
C
A
G
8
u
7
8
o r
. g
, f
0 -
u
1
32
0
p
0
, 2
, f
0
2
1SIO2
0
16
0
5
=1), the main clock division register (address 000C
, f
Page 45
8SIO2
, f
32SIO2
16
16
f o
) to “1” and then executing a WAIT instruction.
").
3
2
9
6
and P8
CIN
IN
-X
-X
OUT
COUT
7
to no pull-up resistance with the input port.
16
drive capacity select bit (bit 5 at address 0007
drive capacity select bit (bit 3 at address 0006
=1) or the mode is shifted to stop mode (bit 0 at
16
) is set to the division by 8 ("08
8. Clock Generating Circuit
16
), the sub clock can be
16
). However, be sure
16
). Switching to
16
16
16
16
) is
").
).
).