M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 49

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
Figure 7.3 ALE signal and address/data bus
Table 7.7 Microcomputer status in ready state (Note)
Note: The ready signal cannot be received immediately prior to a software wait.
6
1 .
0
(4) ALE signal
(5) Ready signal
Oscillation
RD/WR signal, address bus, data bus, CS
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
C
_____ _____
9
0 .
8 /
B
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls. The ALE output pin is selected using bits 4 and 5 of the processor mode register 1
(address 0005
The ALE signal is occurred regardless of internal area and external area.
The ready signal facilitates access of external devices that require a long time for access. As shown in
Figure 7.2, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter the
ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table 7.7
shows the microcomputer status in the ready state. Figure 7.4 shows the example of the RD signal being
extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is ap-
plied. When no software wait is operating, the RDY signal is ignored, but even in this case, unused pins
must be pulled up.
ALE
A
A
D
A
0
0
8
20
0
0
16
1
/A
to A
A
8
G
to A
to A
0
u
7
o r
. g
to D
0 -
15
When BYTE pin = “H”
19
22
u
1
0
p
0
, A
, 2
7
0
__________
/A
23
2
7
0
0
Note 1: Floating when reading.
Note 2: When full space multiplexed bus is selected, these are I/O ports.
16
5
).
Page 36
Address
________
Item
Address
Address (Note 2)
Address or CS
f o
________
3
2
________
9
Data (Note 1)
_____
________
On
Maintain status when ready signal received
On
D
ALE
A
A
0
16
20
/A
to A
to A
0
to D
19
22
When BYTE pin = “L”
, A
15
/A
23
15
Status
Address
Address (Note 2)
Address or CS
Data (Note 1)
_____
7. Bus