M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 229

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
1 .
0
C
9
Additional process
Example 5)
0 .
8 /
B
• To return from an interrupt to the address set in an address match interrupt register using return
0
0
0
instruction (reit or freit)
If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the
below processing to the end of all interrupts.
If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple
interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt
C routines.
Interrupt_A:
1
A
To rewrite the interrupt control register within the interrupt routine, add the below processing to the
end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are
enabled with other interrupts, add the below processing to the end of the interrupt that enables the
multiple interrupts.
8
G
u
7
o r
fclr
pushm R0
mov.w 6[SP],R0
ldc
popm R0
nop
reit
pushm R0,R1,R2,R3,A0,A1
••••
bclr
••••
popm R0,R1,R2,R3,A0,A1
fclr
pushm R0
mov.w 6[SP],R0
ldc
popm R0
nop
reit
. g
0 -
Example 4)
u
1
0
p
0
, 2
0
2
0
ldipl
nop
nop
nop
U
R0,FLG
Interrupt A routine
3,TA0IC
U
R0,FLG
0
5
Page 216
#0
; Rewrite IPL to a smaller value
; 1st instruction
; 2nd instruction
; 3rd instruction
f o
3
2
9
; Execute after the register reset instruction (popm instruction)
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
; Read FLG on stack (use "stc SVF,R0" when high-speed
;
; Set in FLG
; Restore R0 register
; Dummy
; Interrupt completed (use freit when high-speed interrupt)
; Store registers
; Rewrite interrupt control register of interrupt B
; Restore registers
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
; Read FLG on stack
; Set in FLG
; Restore R0 register
; Dummy
; Interrupt completed
Do not set address match interrupt
during this period
interrupt)
27. Usage Precaution