M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 51

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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R
R
e
E
1
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Table 7.8 Microcomputer status in hold state
Table 7.9 External bus status when accessing to internal area
6
Figure 7.5 Example of RD signal extended by RDY signal
1 .
0
__________
Oscillation
RD/WR signal, address bus, data bus, CS, BHE
Programmable I/O ports P0, P1, P2, P3, P4, P5
HLDA
Internal peripheral circuits
ALE signal
________
(6) Hold signal
_____ _____
Note: Ports P11 to P15 exist in 144-pin version.
(7) External bus status when accessing to internal area
Address bus
Data bus When read
RD, WR, WRL, WRH
BHE
CS
ALE
(8) BCLK output
C
_____
____
9
0 .
8 /
B
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 7.8 shows
the microcomputer status in the hold state. The bus is used in the following descending order of priority:
__________
HOLD, DMAC, CPU.
Table 7.9 shows external bus status when accessing to internal area
BCLK output can be selected by bit 7 of the processor mode register 0 (address 0004
and bit 0 of the system clock select register 0 (address 0006
CM01 and CM00 to “00” outputs the BCLK signal from P5
is not output. When setting PM07 to “1”, the function is as set by CM01 and CM00.
0
0
0
1
______
A
8
G
__________
Item
u
7
o r
. g
0 -
u
1
________ _________
0
p
0
When write Floating
, 2
0
2
0
0
5
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_____
Remain address of external area accessed immediately before
Floating
Output "H"
Remain external area status accessed immediately before
Output "H"
ALE output
P6, P7, P8, P9, P10
P11, P12, P13, P14, P15 (Note)
Item
f o
SFR accessing status
3
2
9
__________
HOLD > DMAC > CPU
_____
__________
_______
________
3
ON
Floating
Maintains status when hold signal is received
Output “L”
ON (but watchdog timer stops)
Undefined
. However, in single chip mode, BCLK signal
16
Internal ROM/RAM accessing status
:CM01, CM00). Setting PM07 to “0” and
__________
Status
16
:PM07) and bit 1
7. Bus