M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 293

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
Table 30.1 List of software commands (CPU rewrite mode)
1 .
0
C
Software Commands
Note 1: When a software command is input, the high-order byte of data (D
Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D
Note 6: X denotes a given address in the user ROM area (that is an even address).
Read array
Read status register
Clear status register
Block erase
Lock bit program
Read lock bit status
Page program
Erase all unlock block
9
0 .
8 /
B
Table 30.1 lists the software commands available with the M16C/62A (flash memory version).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D
The content of each software command is explained below.
0
0
Read Array Command (FF
Read Status Register Command (70
Clear Status Register Command (50
0
1
A
The read array mode is entered by writing the command code “FF
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D
The read array mode is retained intact until another command is written.
When the command code “70
read out at the data bus (D
in the user ROM area).
The status register is explained in the next section.
This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
“50
8
G
u
7
Command
WA and WD must be set sequentially from 00
256 bytes.
o r
. g
0 -
6
16
u
corresponds to the block lock status. Block not locked when D
1
0
” in the first bus cycle.
p
0
, 2
0
2
0
0
(Note 3)
5
Page 280
Mode
Write
Write
Write
Write
Write
Write
Write
Write
f o
16
First bus cycle
0
3
–D
2
)
Address
9
X
16
7
(Note 6)
) by a read in the second bus cycle. (Set an address to even address
X
X
X
X
X
X
X
” is written in the first bus cycle, the content of the status register is
16
16
(D
0
)
)
–D
Data
0
FF
A7
70
50
41
20
77
71
16
to D
16
16
16
16
16
16
to FE
16
16
15
), 16 bits at a time.
7
)
16
Write
Write
Write
Write
Read
Read
Mode
(byte address; however, an even address). The page size is
Second bus cycle
WA0
BA
Address
6
8
X
= 1, block locked when D
BA
BA
to D
(Note 6)
(Note 4)
X
(Note 3)
15
) is ignored.
SRD
WD0
(D
D0
D0
D0
D
16
0
Data
16
16
16
6
to D
” in the first bus cycle. When an
(Note 2)
(Note 3)
(Note 5)
7
)
30. CPU Rewrite Mode
Mode Address
Write
6
= 0.
8
Third bus cycle
to D
WA1
15
) is ignored.
(D
0
WD1
Data
to D
7
)