M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 163

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
Figure 18.5 Timing for switching serial data logic
Figure 18.6 Detection timing of a bus collision (in UART mode)
1 .
0
C
9
0 .
8 /
B
0
0
(c) Function for switching serial data logic (UART2 to UART4)
(d) TxD, RxD I/O polarity reverse function (UART2 to UART4)
(e) Bus collision detection function (UART2 to UART4)
0
1
A
When the data logic select bit (bit 6 of address 033D
in writing to the transmission buffer register or reading the reception buffer register. Figure 18.5 shows
the example of timing for switching serial data logic.
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 18.6
shows the example of detection timing of a buss collision (in UART mode).
8
G
interrupt request signal
Bus collision detection
Bus collision detection
u
7
o r
. g
0 -
interrupt request bit
u
1
0
Transfer clock
p
0
• When LSB first, parity enabled, one stop bit
, 2
0
Transfer clock
(no reverse)
2
0
(reverse)
0
5
TxD
TxD
Page 150
RxD
TxD
i
i
i
i
“H”
“H”
“H”
“L”
“L”
“L”
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
“1”
“0”
f o
3
2
9
ST
ST
D0
D0
ST
ST
D1
D1
18. Clock asynchronous serial I/O (UART) mode
D2
D2
D3
D3
16
, 032D
D4
D4
16
D5
D5
, 02FD
D6
D6
16
) is assigned 1, data is inverted
D7
D7
ST : Start bit
P : Even parity
SP : Stop bit
P
P
SP
SP
SP
SP
ST : Start bit
SP : Stop bit