M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 292

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Precautions on CPU Rewrite Mode
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Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
0
0
(1) Operation speed
(2) Instructions inhibited against use
(3) Interrupts inhibited against use
(4) Reset
(5) Access disable
(6) How to access
(7)Writing in the user ROM area
(8)Using the lock bit
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During CPU rewrite mode, set the BCLK as shown below using the main clock division register (ad-
dress 000C
6.25 MHz or less when wait bit (bit 2 at address 0005
12.5 MHz or less when wait bit (bit 2 at address 0005
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can
be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur-
rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer inter-
rupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be
performed over again.
Reset input is always accepted.
Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit
in an area other than the internal flash memory.
For CPU rewrite mode select bit, lock bit disable bit, and flash memory power supply-OFF bit to be set
to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it
is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed
during the interval.
Write to the CPU rewrite mode select bit when NMI pin is "H" level.
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O
mode to rewrite these blocks.
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.
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) = 0 (without internal access wait state)
) = 1 (with internal access wait state)
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30. CPU Rewrite Mode