M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 228

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
1 .
0
C
Interrupts
9
0 .
8 /
B
(1) Setting the stack pointer
(2) The NMI interrupt
(3) Address match interrupt
0
0
0
1
A
G
8
u
7
o r
. g
0 -
• The value of the stack pointer is initialized to 000000
• As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the V
• The NMI pin also serves as P8
• Signals input to NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the
• Do not set the following addresses to the address match interrupt register.
Example 1)
Example 2)
Example 3)
u
1
interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard-
ing the first instruction immediately after reset, generating any interrupts including the NMI inter-
rupt is prohibited.
Set an even address to the stack pointer so that operating efficiency is increased.
_______
resistance (pulled-up) if unused.
register allows reading the pin value. Use the reading of this pin only for establishing the pin level
at the time when the NMI interrupt is input.
operation clock of CPU.
1. The address of the starting instruction in an interrupt routine.
2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt
3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt
4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor
0
p
0
, 2
0
request bit of an interrupt control register or an instruction to rewrite an interrupt priority level to
a smaller value.
enable flag (I flag).
interrupt priority level (IPL) to a smaller value.
2
0
_______
Interrupt_A:
mov.b
nop
nop
nop
nop
nop
nop
nop
fset
nop
nop
nop
0
5
Page 215
_______
pushm R0,R1,R2,R3,A0,A1
••••
I
#0,TA0IC
_______
_______
; 1st instruction
; 2nd instruction
; 3rd instruction
; Set I flag ( interrupt enabled)
f o
_______
3
2
9
;Change TA0 interrupt priority level to a smaller value
; 1st instruction
; 2nd instruction
; 3rd instruction
; 4th instruction
; 5th instruction
; 6th instruction
; 7th instruction
5
, which is exclusively input. Reading the contents of the P8
Do not set address match interrupt
during this period
; Interrupt A routine
; <----
;
Do not set address match interrupt to the
start address of an interrupt instruction
Do not set address match interrupt
during this period
16
immediately after reset. Accepting an
27. Usage Precaution
CC
_______
pin via a