M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 301

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
Functions To Prevent the Flash Memory from Rewriting
e
E
1
v
J
6
Figure 30.9 ROM code protect control address
1 .
0
C
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code verify function for use
in standard serial I/O mode.
ROM code protect function
9
0 .
8 /
B
The ROM code protect function reading out or modifying the contents of the flash memory version by
using the ROM code protect control address (0FFFFFF
the ROM code protect control address (0FFFFFF
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
0
0
0
1
A
8
G
u
7
o r
. g
0 -
ROM Code Protect Control Address
b7
NOTES:
u
1
0
p
0
, 2
b6
1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected
2. Set the bit 5 to bit 0 to "111111
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard
4. The ROMCP address is set to "FF
5. When a value of the ROMCP address is "00
0
against reading or rewriting in parallel I/O mode.
If the bit 5 to bit 0 are set to values other than "111111
active by setting the ROMCP1 bit to a value other than "11
serial I/O mode or CPU rewrite mode.
2
1
b5
0
0
5
b4
1
Page 288
b3
1 1 1 1
b2
b1
b0
f o
ROMCP1
(b5 - b0)
3
Symbol
2
9
Bit
Symbol
ROMCP
2
" when the ROMCP1 bit is set to a value other than "11
Reserved Bit
ROM Code Protect
Level 1 Set Bit
16
" when a block, including the ROMCP address, is erased.
Bit Name
16
Address
FFFFFF
" or "FF
16
(1, 2, 3, 4)
(5)
). (This address exists in the user ROM area.)
16
2
16
16
", the ROM code protection may not become
", the ROM code protect function is disabled.
) during parallel I/O mode. Figure 30.9 shows
2
b7 b6
0 0 : ROM code protection active
0 1 : ROM code protection active
1 0 : ROM code protection active
1 1 : ROM code protection inactive
Set to "1"
".
Factory Setting
FF
Function
16 (4)
2
".
30. CPU Rewrite Mode
RW
RW
RW