M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 264

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
v
J
6
Timing requirements (referenced to V
Table 28.24 External clock input
Table 28.25 Memory expansion and microprocessor modes
Note: Calculated according to the BCLK frequency as follows:
1 .
t
t
0
t
t
t
t
t
t
t
t
t
C
t
t
t
t
t
t
su(DB-BCLK)
su(RDY-BCLK )
su(HOLD-BCLK )
h(BCLK -RDY)
h(BCLK-HOLD )
h(RD-DB)
h(CAS-DB)
d(BCLK-HLDA )
t
t
ac2(RD-DB)
ac2(AD-DB)
ac3(RD-DB)
ac3(AD-DB)
ac4(CAD-DB)
t
t
t
ac1(RD-DB)
ac1(AD-DB)
ac4(RAS-DB)
ac4(CAS-DB)
9
0 .
Symbol
c
w(L)
f
w(H)
r
Symbol
8 /
B
0
0
0
1
A
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
G
8
u
7
t
t
o r
t
t
t
t
t
t
t
. g
ac4(RAS – DB)
ac4(CAS – DB)
0 -
ac1(RD – DB)
ac2(RD – DB)
ac4(CAD – DB)
ac1(AD – DB)
ac2(AD – DB)
ac3(RD – DB)
ac3(AD – DB)
u
1
0
p
0
, 2
External clock rise time
External clock input LOW pulse width
External clock input cycle time
External clock input HIGH pulse width
External clock fall time
0
2
0
0
HOLD input setup time
RDY input hold time
Data input access time (RD standard, no wait)
Data input access time (RD standard, with wait)
Data input access time
Data input access time
multiplex bus area)
Data input access time (RAS standard, DRAM access)
Data input access time (CAS standard, DRAM access)
Data input setup time
RDY input setup time
Data input hold time
HOLD input hold time
HLDA output delay time
Data input access time (AD standard, CS standard, no wait)
Data input access time (AD standard, CS standard, with wait)
Data input access time (CAD standard, DRAM access)
Data input hold time
5
=
=
=
=
=
=
=
=
Page 251
=
f
f
f
f
(BCLK)
(BCLK)
(BCLK)
(BCLK)
f
10 X m
f
10 X n
f
10 X m
10 X n
f
(BCLK)
(BCLK)
(BCLK)
(BCLK)
10 X m
10 X l
10 X n
f
10
10
9
9
(BCLK)
9
9
9
9
9
9
9
X 2
X 2
X 2
X 2
X 2
X 2
f o
– 55
– 55
– 55
– 42
– 42
– 55
3
2
– 55
– 55
– 55
9
Parameter
(AD standard, CS standard, when accessing
(RD standard, when accessing multiplex bus area)
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
[ns]
[ns]
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
CC
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
[ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
Parameter
= 3V, V
SS
= 0V at Topr = 25
o
C unless otherwise specified)
Min.
100
28. Electrical characteristics
40
40
Standard
Min.
40
60
80
Standard
0
0
0
0
Max.
18
18
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Max.
100
V
Unit
ns
ns
ns
ns
ns
Unit
CC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 3V