M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 87

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
9.22 Precautions for Interrupts
e
E
1
v
J
6
1 .
0
(1) Reading addresses 000000
(2) Setting the stack pointer
(3) The NMI interrupt
(4) External interrupt
C
9
0 .
8 /
B
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
• The value of the stack pointer immediately after reset is initialized to 000000
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistance
• The NMI pin also serves as P8
• Signals input to the NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the
• Edge sense
• Level sense
• When the polarity of the INT
0
0
0
interrupt request level) in the interrupt sequence from address 000000
is occurred, CPU read from address 000002
The interrupt request bit of the certain interrupt will then be set to “0”.
However, reading addresses 000000
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
at the beginning of a program. Any interrupt including the NMI interrupt is generated immediately after
executing the first instruction after reset. Set an even address to the stack pointer so that the operating
efficiency of accessign memory is increased.
(pull-up) if unused. Be sure to work on it.
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
when the NMI interrupt is input.
operation clock of CPU.
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT
to INT
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT
mode, at least 250 ns width is necessary.)
After changing the polarity, set the interrupt request bit to "0". Figure 9.12 shows the procedure for
changing the INT interrupt generate factor.
1
A
8
G
u
7
o r
. g
0 -
_______
u
_______
1
5
0
p
0
, 2
regardless of the CPU operation clock.
0
2
_______
_______
0
0
5
______
Page 74
0
to INT
______
5
f o
regardless of the CPU operation clock. (When X
0
3
2
to INT
9
5
, which is exclusively input. Reading the contents of the P8 register
16
5
pins is changed, the interrupt request bit is sometimes set to "1".
16
and 000002
and 000002
16
.
16
16
by software does not set request bit to “0”.
_______
_______
16
. When high-speed interrupt
IN
16
=20MHz and no division
. Accepting an interrupt
9. Interrupt Outline
0