M30802FCGP#D3 Renesas Electronics America, M30802FCGP#D3 Datasheet - Page 73

• Manufacturer Part Number: M30802FCGP#D3
• Description: IC M16C MCU FLASH 128K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30802FCGP#D3

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Table 9.1 Interrupt factors (fixed interrupt vector addresses)
6
Table 9.2 Interrupt vector table register for emulator
1 .
0
Interrupt source
_______
Interrupt source
Undefined instruction
Overflow
BRK instruction
execution
Address match
Watchdog timer
NMI
Reset
C
BRK2 instruction
Single step
9
0 .
8 /
B
0
• Fixed vector tables
• Vector table dedicated for emulator
• Variable vector tables
0
0
1
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFFDC
of interrupt routine in each vector table. Table 9.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 9.2 shows interrupt vector address which is vector table register dedicated for emulator (ad-
dress 000020
(non maskable interrupt).
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. Do not access to the interrupt vector table register dedicated for emulator (address 000020
000022
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 9.3 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Set an even address to the start address of vector table setting in INTB so that operating efficiency is
increased.
A
8
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7
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1
0
p
0
, 2
0
16
2
0
).
0
5
Page 60
16
to 000022
Address (L) to address (H)
Interrupt vector table register for emulator
000020
Interrupt vector table register for emulator
000020
FFFFDC
FFFFE8
FFFFFC
FFFFE0
FFFFE4
FFFFF8
FFFFF0
Vector table addresses
16
f o
to FFFFFF
16
16
3
16
16
16
2
16
16
16
16
16
Address (L) to address (H)
9
). These instructions are not effected with interrupt enable flag (I flag)
to 000022
to 000022
to FFFFEB
to FFFFFB
Vector table addresses
to FFFFE3
to FFFFE7
to FFFFDF
to FFFFF3
to FFFFFF
16
. One vector table comprises four bytes. Set the first address
16
16
16
16
16
16
16
16
16
Interrupt on UND instruction
Interrupt on INTO instruction
If content of FFFFE7
starts from the address shown by the vector in the
variable vector table
There is an address-matching interrupt enable bit
External interrupt by input to NMI pin
Interrupt for debugger
Interrupt for debugger
Remarks
16
is filled with FF
_______
Remarks
9. Interrupt Outline
16
, program
16
to