am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 104

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1-578
SYSTEM APPLICATION
ISA Bus Interface
Compatibility Considerations
Although 8 MHz is now widely accepted as the standard
speed at which to run the ISA bus, many machines have
been built which operate at higher speeds with non-
standard timing. Some machines do not correctly
support 16-bit I/O operations with wait states. Although
the PCnet-ISA
still require an occasional wait state. The PCnet-ISA
controller moves data through memory accesses, there-
fore, I/O operations do not affect performance. By
configuring the PCnet-ISA
vice, compatibility with PC/AT-class machines is
obtained at virtually no cost in performance. To treat the
PCnet-ISA
non-ISA applications), the even-byte must be accessed
first, followed by an odd-byte access.
Memory cycle timing is an area where some tradeoffs
may be necessary. Any slow down in a memory cycle
translates
PCnet-ISA
bandwidth than most slave type controllers and should
continue to be superior even if an extra 50 or 100 ns are
added to memory cycles.
The memory cycle active time is tunable in 50 ns incre-
ments with a default of 250 ns. The memory cycle idle
time defaults to 200 ns and can be reprogrammed to
100 ns. See register description for ISACS42. Most ma-
chines should not need tuning.
The PCnet-ISA
and NE1500T software drivers. All the resources such
AMD
Bus
ISA
+
+
16-Bit System Data
controller as an 8-bit software resource (for
directly
controller starts out with much higher
24-Bit System
+
+
controller is quite fast, some operations
Address
controller is compatible with NE2100
into
+
controller as an 8-bit I/O de-
lower
SD[0-15]
SA[0-19]
LA[17-23]
PCnet-ISA
Controller
bandwidth.
SHFBUSY
Bus Master Block Diagram
Plug and Play Compatible
BPCS
+
P R E L I M I N A R Y
PRDB[2]/EEDO
PRDB[0]/EESK
PRDB[1]/EEDI
VCC
The
Am79C961
PRDB[0-7]
+
EECS
as address PROM, boot PROM, RAP, and RDP are in
the same location with the same semantics. An addi-
tional set of registers (ISA CSR) is available to configure
on board resources such as ISA bus timing and LED op-
eration. However, loopback frames for the PCnet-ISA+
controller must contain more than 64 bytes of data if the
Runt Packet Accept feature is not enabled; this size limi-
tation does not apply to LANCE (Am7990) based boards
such as the NE2100 and NE1500T.
Bus Master
Bus Master mode is the preferred mode for client appli-
cations on PC/AT or similar machines supporting 16-bit
DMA with its unsurpassed combination of high perform-
ance and low cost.
Shared Memory
The shared memory mode is recommended for file serv-
ers or other applications where there is very high,
average or peak latency.
The address compare circuit has the following
functions. It receives the 7 LA signals, generates
MEMCS16, and compares them to the desired shared
memory and boot PROM addresses. The logic latches
the address compare result when BALE goes inactive
and uses the appropriate SA signals to generate SMAM
and BPAM.
All these functions can be performed in one PAL device.
To operate in an 8-bit PC/XT environment, the LA
signals should have weak pull-down resistors con-
nected to them to present a logic 0 level when not driven.
VCC
DO
DI
SK
CS
ORG
D[0-7]
A[0-15]
CE
EEPROM
PROM
Boot
OE
18183B-6