am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 58

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

Carrier Tracking and End of Message
The carrier detection circuit monitors the DI inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS deassert allows the last bit to
be strobed by IRXCLK and transferred to the controller
section, but prevents any extra bit(s) at the end of mes-
sage. When IRXCRS de-asserts an IRXCRS hold off
timer inhibits IRXCRS assertion for at least 2 bit times.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI inputs. Input error is
less than
and fall time. IRXCLK strobes the data receiver output at
1/4 bit time to determine the value of the Manchester bit,
and clocks the data out on IRXDAT on the following
IRXCLK. The data receiver also generates the signal
used for phase detector comparison to the internal
MENDEC voltage controlled oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI )
should be externally terminated by two 40.2
sistors and one optional common-mode bypass
capacitor, as shown in the Differential Input Termination
diagram below. The differential input impedance, Z
and the common-mode input impedance, Z
specified so that the Ethernet specification for cable ter-
mination impedance is met using standard 1% resistor
terminators. If SIP devices are used, 39
usable equivalent value. The CI differential inputs are
terminated in exactly the same way as the DI pair.
1-532
PCnet-ISA
PCnet-ISA
AMD
DI+
DI-
+
Differential Input Termination
35 mV to minimize sensitivity to input rise
40.2
0.01 F
to 0.1 F
40.2
AUI Isolation
Transformer
18183B-16
is the nearest
16907B-9
P R E L I M I N A R Y
ICM
1% re-
, are
IDF
Am79C961
,
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI inputs. This
collision signal passes through an input stage which de-
tects signal levels and pulse duration. When the signal is
detected by the MENDEC it sets the internal collision
signal, ICLSN, HIGH. The condition continues for ap-
proximately 1.5 bit times after the last LOW-to-HIGH
transition on CI .
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in the
pattern.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of “Jitter Han-
dling” is:
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which con-
nects the DTE to a MAU. The differential interface
provided by the PCnet-ISA
with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-ISA
it will expect to see data “looped-back” on the DI pair
(when the AUI port is selected). This will internally
generate a “carrier sense”, indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted within sometime before end of trans-
mission. If “carrier sense” does not become active in
response to the data transmission, or becomes inactive
before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Descriptor
Ring (TMD3, bit 11) after the packet has been
transmitted.
Twisted Pair Transceiver (T-MAU)
The T-MAU implements the Medium Attachment Unit
(MAU) functions for the Twisted Pair Medium, as speci-
fied by the supplement to IEEE 802.3 standard (Type
10BASE-T). The T-MAU provides twisted pair driver
and receiver circuits, including on-board transmit digital
predistortion and receiver squelch, and a number of ad-
ditional features including Link Status indication,
Automatic Twisted Pair Receive Polarity Detection/
Correction and Indication, Receive Carrier Sense,
Transmit Active and Collision Present indication.
The peak deviation approaching or crossing 1/4
bit cell position from nominal input transition, for
which the MENDEC section will properly de-
code data.
+
controller initiates a transmission,
+
controller is fully compliant