am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 17

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

IRQ 3, 4, 5, 9, 10, 11, 12, 15
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.
All status flags have a mask bit which allows for
suppression of IRQ assertion. These flags have the fol-
lowing meaning:
Because of the operation of the Plug and Play registers,
the interrupts on the PCnet-ISA
specific IRQ signals on the PC/AT bus.
LA17-23
Unlatched Address Bus
The unlatched address bus is driven by the PCnet-ISA
controller during bus master cycle.
The functions of these unlatched address pins will
change when GPSI mode is invoked. The following ta-
ble shows the pin configuration in GPSI mode. Please
refer to the section on General Purpose Serial Interface
for detailed information on accessing this mode.
MASTER
Master Mode
This signal indicates that the PCnet-ISA
become the Current Master of the ISA bus. After the
PCnet-ISA
edge (DACK) in response to a DMA Request (DRQ), the
Ethernet controller asserts the MASTER signal to indi-
cate to the Permanent Master that the PCnet-ISA
controller is becoming the Current Master.
MEMR
Memory Read
MEMR goes LOW to perform a memory read operation.
BABL
RCVCCO
JAB
MISS
MERR
MPCO
RINT
IDON
TXDATSTRT
Number
Pin
10
11
12
13
15
16
17
+
controller has received a DMA Acknowl-
Bus Master Mode
Pin Function in
Babble
Receive Collision Count Overflow
Jabber
Missed Frame
Memory Error
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
LA17
LA18
LA19
LA20
LA21
LA22
LA23
+
must be attached to
Output
Input/Output
Input/Output
Input/Output
Pin Function in
GPSI Mode
SRDCLK
STDCLK
RXCRS
+
RXDAT
TXDAT
CLSN
TXEN
controller has
P R E L I M I N A R Y
Am79C961
+
+
MEMW
Memory Write
MEMW goes LOW to perform a memory write
operation.
REF
Memory Refresh
When REF is asserted, a memory refresh is active. The
PCnet-ISA
tent DMA Acknowledge assertion during memory
refresh periods. If DACK is asserted when REF is ac-
tive, DACK assertion is ignored. REF is monitored to
eliminate a bus arbitration problem observed on some
ISA platforms.
RESET
Reset
When RESET is asserted HIGH the PCnet-ISA
ler performs an internal system reset. RESET must be
held for a minimum of 10 XTAL1 periods before being
deasserted. While in a reset state, the PCnet-ISA+ con-
troller will tristate or deassert all outputs to predefined
reset levels. The PCnet-ISA
upon power-up.
SA0-19
System Address Bus
This bus contains address information, which is stable
during a bus operation, regardless of the source.
SA17-19 contain the same values as the unlatched ad-
dress LA17-19. When the PCnet-ISA
Current Master, SA0-19 will be driven actively. When
the PCnet-ISA
SA0-19 lines are continuously monitored to determine if
an address match exists for I/O slave transfers or Boot
PROM accesses.
SBHE
System Byte High Enable
This signal indicates the high byte of the system data
bus is to be used. SBHE is driven by the PCnet-ISA
controller when performing bus mastering operations.
SD0-15
System Data Bus
These pins are used to transfer data to and from the
PCnet-ISA
data bus. SD0-15 is driven by the PCnet-ISA
when performing bus master writes and slave read op-
erations. Likewise, the data on SD0-15 is latched by the
PCnet-ISA
reads and slave write operations.
Board Interface
IRQ12/FlashWE
Flash Write Enable
Optional interface to the Flash memory boot PROM
Write Enable.
+
+
+
controller uses this signal to mask inadver-
controller to system resources via the ISA
controller when performing bus master
+
controller is not the Current Master, the
+
controller resets itself
Input/Output
Input
Input
Input/Output
Input/Output
Input/Output
Output
+
controller is the
+
AMD
controller
+
control-
1-491
+